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JPS63296221A - Formation of resist pattern - Google Patents

Formation of resist pattern

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Publication number
JPS63296221A
JPS63296221A JP13425387A JP13425387A JPS63296221A JP S63296221 A JPS63296221 A JP S63296221A JP 13425387 A JP13425387 A JP 13425387A JP 13425387 A JP13425387 A JP 13425387A JP S63296221 A JPS63296221 A JP S63296221A
Authority
JP
Japan
Prior art keywords
pattern
resist
resist pattern
mask
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13425387A
Other languages
Japanese (ja)
Inventor
Toru Koyama
徹 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13425387A priority Critical patent/JPS63296221A/en
Publication of JPS63296221A publication Critical patent/JPS63296221A/en
Pending legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain the sufficient thermal resistance by using UV curing device of a low-output light source without a need for a long-hour process and for an investment in plant and equipment by a method wherein a groove whose depth is less than a thickness of a resist pattern is formed inside the resist pattern. CONSTITUTION:A positive-type photoresist film 2 is formed on a substrate 1 to be processed. Then, an exposure operation is executed via a mask to which a vacant pattern 4 whose size is less than a limit of resolution of the resist film 2 is attached. Then, after a development operation, UV curing operation is executed by irradiation with UV rays 6 while the substrate is being heattreated 7 and a resist pattern having a groove whose depth is less than a thickness of the pattern is formed inside the resist pattern. By this setup, an area of a resist-hardening layer 2d on the surface is expanded after the UV process and the layer becomes strong structurally against internal stress. Accordingly, it is possible to obtain the sufficient thermal resistance by using a UV curing device of a low-output light source and to achieve the desired purpose.

Description

【発明の詳細な説明】 〔産業上の利用分野J この発明は、レジストパターンの形成方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J This invention relates to a method for forming a resist pattern.

〔従来の技術J 第5図はポジ型フォトレジストによるレジスト/4ター
ン形成方法において、現像処理後以降の工程のa行に伴
うレジストパターンの断面図である。
[Prior Art J] FIG. 5 is a cross-sectional view of a resist pattern along line a in the steps after development processing in a resist/four-turn forming method using a positive photoresist.

第5図(a)は被加工基板l上にポジレジストを塗布し
、プリベーク後、所定のパターンを選択的に露光し、現
像処理を行なうことによって得られたレジストパターン
の断面図を示す。第5図(b)はUVキュア処理を示し
、6Fi紫外光、7I/i基板加熱を示している。尚、
7の基板加熱は併用されない場合もある。2dはUVキ
ュア処理により、光架橋反応が生じ硬質化したレジスト
の硬化部分を示し、2cは本硬化部分を示す。第5図(
c) Fiポストベーク処理を示し、9は加熱を示す。
FIG. 5(a) shows a cross-sectional view of a resist pattern obtained by applying a positive resist onto a substrate 1 to be processed, prebaking, selectively exposing a predetermined pattern, and performing a development process. FIG. 5(b) shows UV curing treatment, showing 6Fi ultraviolet light and 7I/i substrate heating. still,
Substrate heating in step 7 may not be used together. 2d indicates a hardened portion of the resist that has undergone a photo-crosslinking reaction and hardened due to UV curing treatment, and 2c indicates a fully cured portion. Figure 5 (
c) Fi indicates post-bake treatment, 9 indicates heating.

加熱はオーブンやホットプレートによって行なわれる。Heating is done using an oven or hot plate.

ポジ型フォトレジストの耐熱性及び、1IiFtプラズ
マエツチング性の向上を目的として、UVキュア処理が
一般的に行なわれている。VUキュア処理は、第5図(
b)に示す様に1通常、基板加熱をしながらUV光をレ
ジストに照射することにより、レジストに光架橋反応を
生じさせ、レジストを硬化させることによって上記の目
的を達成させる。UVキュアによるレジストの硬化部分
は、レジスト表面から内部へ進行する。硬化部分の進行
が不十分であれば、ポストベーク処理時、あるいは、プ
ラズマエツチング処理時に、第5図(Q)の様に、熱に
よる内部応力により、パターン形状を維持できず、パタ
ーンが変形してしまう。レジストパターンの変形は、プ
ラズマエツチング後のエツチングパターンの寸法変助を
もたらし、寸法制御性も低下させることになる。レジス
トの高解像度化が進む中で鵠脂分子盪は、低分子化傾向
にあり、それに伴って、UVキュアによる硬化部の生成
速度が減少し、硬化部の生成が困難になってさている。
UV curing treatment is generally performed for the purpose of improving the heat resistance and 1IiFt plasma etching properties of positive photoresists. The VU cure process is shown in Figure 5 (
As shown in b), the above objective is usually achieved by irradiating the resist with UV light while heating the substrate to cause a photocrosslinking reaction in the resist and harden the resist. The hardened portion of the resist by UV curing progresses from the resist surface to the inside. If the progress of the hardened portion is insufficient, the pattern shape may not be maintained due to internal stress due to heat during post-baking processing or plasma etching processing, and the pattern may become deformed, as shown in Figure 5 (Q). It ends up. Deformation of the resist pattern causes dimensional changes in the etched pattern after plasma etching, and also reduces dimensional controllability. As the resolution of resists progresses, resin molecules tend to have lower molecular weights, and as a result, the rate at which cured areas are formed by UV curing is reduced, making it difficult to form cured areas.

その為、UVキュア処理の長時間化及び、光源の高出力
化が必要になり、地理能力の低下や、設備投資が避けら
れなくなってきている。
Therefore, it becomes necessary to take a longer time for UV curing treatment and to increase the output of the light source, which makes it inevitable to reduce geographic capacity and require capital investment.

一方、レジストの硬化部の成長に伴って、レジスト除去
は困難になる。従って、UVキュア処理を過剰に行なえ
ば、除去処理の長時間化を招き、下地基板へのダメージ
が大きくなるといった問題が生じて来る。
On the other hand, as the hardened portion of the resist grows, it becomes difficult to remove the resist. Therefore, if the UV curing process is performed excessively, the removal process will take a long time, leading to problems such as increased damage to the underlying substrate.

〔発明が解決しようとする問題点1 以上のように、従来例においてはUVキュア処理によっ
て形成されるポジ型フォトレジストの硬化部の成長が不
充分な場合には、ポストベーク処理あるいは、プラズマ
エツチング6理時点で、レジストパターンが変形し、寸
法制御性が低下するといった問題があり九。前記、問題
点を改善するには、UVキュア処理の長時間化に伴う処
理能力の低下又は、光源の高出力化に伴う、設備投資が
避けられない。又、一方で、UVキュア処理を過剰に行
なえば除去処理が困難になるといった問題点がめった。
[Problem to be Solved by the Invention 1] As described above, in the conventional example, if the hardened portion of the positive photoresist formed by UV curing treatment is insufficiently grown, post-bake treatment or plasma etching is performed. 6. At the time of processing, the resist pattern is deformed and dimensional controllability is reduced.9. In order to improve the above-mentioned problems, it is inevitable to reduce the processing capacity due to the longer UV curing process or to invest in equipment due to the increase in the output of the light source. On the other hand, if the UV curing treatment is performed excessively, the removal treatment becomes difficult.

この発明は、上記のような問題点を解決し、低出力光源
のUVキュア装置にて、処理の長時間化、設備投資を必
要とせずに十分な#熱性を得ると共に、レジスト除去処
理の困難化を招かないレジストパターン形成方法を得る
ことを目的とする。
This invention solves the above-mentioned problems, and uses a UV curing device with a low-power light source to obtain sufficient #thermal properties without requiring long processing times or equipment investment, and also solves the difficulty of resist removal processing. The object of the present invention is to obtain a resist pattern forming method that does not cause oxidation.

〔問題点を解決するための手段〕[Means for solving problems]

この発明においては、レジストにパターンを転写するマ
スクの個々のパターン内部に、被加工基板上で、使用す
るポジレジストの解像限界寸法以下になる様な空きパタ
ーンを付加することにより、現像処理後のレジストパタ
ーン内にパターンの厚み以下の深さの溝を形成し、上記
の目的を達成しようとするものである。
In this invention, by adding an empty pattern on the substrate to be processed inside each pattern of the mask that transfers the pattern to the resist, the size is equal to or smaller than the resolution limit dimension of the positive resist used. In this method, grooves having a depth equal to or less than the thickness of the pattern are formed in the resist pattern to achieve the above object.

〔作用〕[Effect]

第4図に従来のレジストパターンとレジストパターン内
に溝を入れた場合のUVキュア処理後のパターンの断面
凶を示す。第4図(a)は、従来のパターンを示し、第
4図(b) dパターン内に溝を入れたものを示す。2
d#−tレジストの硬化部分、2aは未硬化部分、(8
)は内部応力を示す。硬化S分の厚み及びr、レジスト
パターンの厚みが(a)% (b)共に同じであれば、
パターン内に溝がある(b)の方が、パターンの内部容
積が、小さいにもかかわらず硬化部分の容積が大きい為
、従来の(a)に比べて、内部応力に対して、構造的に
強いと言える。内部応力が、パターン形状を維持する力
よりも大きくなれば、その内S応力はパターンを変形さ
せることにより解消される。(第5図(0)参照)その
為、同じ照射エネルギーにて、UVキュア処理をした場
合には、パターン内部に溝を有する(b)の方が耐熱性
は高くなる。
FIG. 4 shows cross-sectional defects of a conventional resist pattern and a pattern in which grooves are formed in the resist pattern after UV curing treatment. FIG. 4(a) shows a conventional pattern, and FIG. 4(b) shows a pattern in which a groove is inserted into the pattern. 2
d#-t hardened part of resist, 2a is uncured part, (8
) indicates internal stress. If the thickness of the cured S portion, r, and the thickness of the resist pattern are (a)% (b) both the same,
(b), which has grooves in the pattern, has a larger volume of the hardened part even though the internal volume of the pattern is smaller, so it is structurally more resistant to internal stress than the conventional pattern (a). It can be said that it is strong. If the internal stress becomes larger than the force that maintains the pattern shape, the internal S stress is eliminated by deforming the pattern. (See FIG. 5(0)) Therefore, when UV curing is performed with the same irradiation energy, the pattern (b) having grooves inside the pattern has higher heat resistance.

第3図に、従来の場合と、レジストパターン内に溝を入
れる場合のマスクパターンの例を示す。
FIG. 3 shows examples of mask patterns in the conventional case and in the case of forming grooves in the resist pattern.

第3図(a)は従来のライン状及び、円形状の場合のマ
スクパターンの例を示しており、3Fiマスク材料とし
て通常使用されているクロムの部分である。
FIG. 3(a) shows examples of conventional mask patterns in the case of a line shape and a circular shape, which are chromium portions that are normally used as a 3Fi mask material.

第3図軸〕はレジストパターン内に溝を入れる場合にオ
ケるマスクパターンの例を示している。3はクロムの部
分を示し、4はパターン内部に付加された空きパターン
の部分を示している。第2図は、従来のマスクを使用し
た場合と、マスクパターン内部に空きパターンを有する
マスクを使用した場合における菖光6理時のポジ型フォ
トレジストの感光状況を示している。第2図(、)は従
来のマスクを使用した場合を示し、第2図(b) //
iマスクパターン同部に空きパターンを有するマスクを
使用した場合を示す。図で、2aはレジストの感光部分
、2bは未感光部分を示し、5#−iレジストの感光波
長光を示す。又、3.4Vi第3図と同じである。第2
図(b)の様に、マスクパターン内部の空きパク−ン4
の寸法か、使用するポジ型7オトレジストの解像限界寸
法よりも狭ければ、レジストの感光部は、レジストの底
口まで到達せず、不完全に終る。
The axis in FIG. 3 shows an example of a mask pattern that can be used when forming grooves in a resist pattern. 3 indicates a chrome portion, and 4 indicates an empty pattern portion added inside the pattern. FIG. 2 shows the exposure state of a positive photoresist during iris photolithography when a conventional mask is used and when a mask having an empty pattern inside the mask pattern is used. Figure 2 (,) shows the case where a conventional mask is used, and Figure 2 (b) //
A case is shown in which a mask having an empty pattern in the same area as the i-mask pattern is used. In the figure, 2a indicates the exposed portion of the resist, 2b indicates the unexposed portion, and indicates the sensitive wavelength light of the 5#-i resist. Also, it is the same as 3.4Vi Fig. 3. Second
As shown in figure (b), there is an empty hole 4 inside the mask pattern.
If the dimension is narrower than the resolution limit dimension of the positive type 7 photoresist used, the exposed area of the resist will not reach the bottom of the resist and will be incomplete.

この状態のレジストを現像処理すると、感光S分のみレ
ジストが除去される為、パターンの厚み以下の深さの溝
を有するレジストパターンを形成できる。
When the resist in this state is developed, the resist is removed by the amount of exposure S, so that a resist pattern having grooves with a depth equal to or less than the thickness of the pattern can be formed.

〔実施例J 第1図は、この発明の一実施例を示したものであり、レ
ジスト塗布処理後から、UVキュア処理に至るまでの各
工程順の断面図である。1中、1〜7は、第2図〜第5
図と同じである。
[Example J FIG. 1 shows an example of the present invention, and is a cross-sectional view of each step from the resist coating process to the UV curing process. 1, 1 to 7 are from Figures 2 to 5.
Same as the figure.

第1図(a)は塗布処理によりポジ型7オトレジストの
膜2を被加工基板1上に形成したところである。第1図
(b)はマスクパターン内に使用するレジスト2の解像
限界寸法以下の空きパターンを付加したマスクを介して
露光処理を行なったところである。図で、3はマスクパ
ターンのクロムのS+を示し、4はマスクパターン内に
付加された空きパターンを示す。又、2aFiレジスト
の感光部分を示し、 2bI−i未感光部分を示す。4
1図(e)は現像処理後のレジストパターンの断面形状
を示している。
FIG. 1(a) shows a state in which a film 2 of positive type 7 photoresist is formed on a substrate 1 to be processed by a coating process. FIG. 1(b) shows the exposure process performed through a mask to which an empty pattern smaller than the resolution limit dimension of the resist 2 used in the mask pattern is added. In the figure, 3 indicates chrome S+ of the mask pattern, and 4 indicates an empty pattern added within the mask pattern. Also, the exposed portion of the 2aFi resist is shown, and the unexposed portion of the 2bI-i resist is shown. 4
FIG. 1(e) shows the cross-sectional shape of the resist pattern after the development process.

第1図(d) I/′i、従来技術(第5図(b)参照
)と同じく基板加熱7を行ないなから紫外光6の照射を
行なうUVキュア処理を示しており、2diz処理によ
って形成されたレジストの硬化部分を示し%2+にを未
硬化部分を示す。
Figure 1(d) I/'i, shows UV curing treatment in which the substrate is heated 7 and then irradiated with ultraviolet light 6, as in the prior art (see Figure 5(b)), and the substrate is formed by 2diz treatment. %2+ indicates the cured portion of the resist, and %2+ indicates the uncured portion.

上記の方法により、レジストパターン内にパターンの厚
み以下の溝を有するレジストパターンが形成され1次に
、引き続きボストベーク処理を行なつ念ところ、レジス
トパターンの変形等は見られず、#:来の方法と比べて
明らかに#熱性の向上が成されていることが確認され念
。更に、プラズマ処理によるレジストパターンの変形、
レジスト膜板9の増加等の異常も見られず、酸素プラズ
マによるレジスト除去処理にも異常//itM認されな
かった。
By the above method, a resist pattern having grooves less than the thickness of the pattern is formed in the resist pattern, and then a post bake process is performed.As a matter of fact, no deformation of the resist pattern was observed. It was confirmed that the thermal properties were clearly improved compared to the above. Furthermore, the deformation of the resist pattern by plasma treatment,
No abnormalities such as an increase in the number of resist film plates 9 were observed, and no abnormalities were observed in the resist removal process using oxygen plasma.

尚、上記第1図では、JI光装置として等倍投影露光装
置を使用したが、縮小投影露光装置を使用すれば、縮小
倍率分だけ、マスクのパターンサイズは拡大できる為、
パターン内に付加する室さパターンの作成は容易になる
In Fig. 1 above, a same-magnification projection exposure device is used as the JI optical device, but if a reduction projection exposure device is used, the pattern size of the mask can be enlarged by the reduction magnification.
It becomes easy to create a chamber pattern to be added within the pattern.

又、上記第1図ではレジストパターン内に溝を1つだけ
設けたが、複数の溝を設ければ更に前記の効果を向上さ
せることができる。
Further, in FIG. 1, only one groove is provided in the resist pattern, but the above effect can be further improved by providing a plurality of grooves.

更に、上記第1図では、溝の方向をパターンに対して同
一方向に形成したが、溝の間隔を考慮すれば、溝の方向
はパターンに対してどんな方向でも良く、例えば、垂直
方向でも斜め方向でも又それらの併用でも、前記と同様
の幼果を得ることかできる。
Furthermore, in FIG. 1 above, the grooves are formed in the same direction with respect to the pattern, but considering the interval between the grooves, the grooves may be in any direction with respect to the pattern, for example, vertically or diagonally. Young fruits similar to those described above can be obtained either in the direction or in combination.

〔発明の幼果] 以上の如くこの発明によれば、被加工基板上に所定のポ
ジレジストパターンを形成する方法において、マスクの
悶々のパターン内部に被加工基板上で、使用するポジレ
ジストの解像限界寸法以下Pてなる様な牽きパターンを
付加することにより、現像処理後のレジストパターン内
にパターンの厚み以下の閑さの溝を形成したので、UV
キュア処J1.rt来のパターンと比べてレジストパタ
ーンの断面積に占めるレジストの表面硬化層の面積か増
大し、内部応力に対して構造的に強靭になる。
[Effects of the Invention] As described above, according to the present invention, in a method for forming a predetermined positive resist pattern on a substrate to be processed, a solution of the positive resist to be used is formed on the substrate to be processed inside the pattern of the mask. By adding a drag pattern that is less than the image limit dimension, we have created a groove that is less than the thickness of the pattern in the resist pattern after development, making it possible to prevent UV rays.
Cure J1. The area of the surface hardened layer of the resist that occupies the cross-sectional area of the resist pattern is increased compared to the pattern from the RT pattern, and the resist pattern becomes structurally strong against internal stress.

その為、UVキュア処理において、光源の高出力及び、
処理の長時間化を必要とせず、設備投資、装置処理能力
の低下を招かすにレジストの耐熱性及び、耐プラズマエ
ツチング性の向上が図れる。
Therefore, in UV curing treatment, the high output of the light source and
It is possible to improve the heat resistance and plasma etching resistance of the resist without requiring a long processing time, which would otherwise lead to a reduction in equipment investment and equipment processing capacity.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例を示すポジ型7オトンジ
ストのパターン形成方法の工程順断面図、第2図は露光
処理におけるこの発明の従来方法との相濾の断面図を示
し、第3凶はマスクパターンにおけるこの発明の従来と
の相違の11rl11]図を示しそおり、第4図はUV
キュア処理後のレジストパターンの断面構造におけるこ
の発明の従来との相濾の断面図を示し、第5図は従来の
ポジ型フォトレジストのパターン形成方法の工程順断面
図である。 図において、1け被加工基&、2けポジ型フォトレジス
ト膜、2a#−1ルジストの感光部分、 2bViレジ
ストの未感光部分、2cはレジストの未硬化部分、2d
ハレジストの硬化部分、3はマスクパターンのクロムパ
ターンの部分、4はマスクパターン内の空きパターンの
部分、5はレジストの感光彼氏光、6は紫外光、7は基
板加熱、8#:l:熱による内部応力、9は加熱である
。 なお、図中、同一符号は同一または相当部分を示す。
FIG. 1 is a step-by-step cross-sectional view of a pattern forming method for a positive type 7-otonist showing an embodiment of the present invention, FIG. Figure 3 shows the difference between this invention and the conventional mask pattern in Figure 11rl11], and Figure 4 shows the difference between the mask pattern and the conventional one.
A cross-sectional view of a phase filter according to the present invention and a conventional method in the cross-sectional structure of a resist pattern after curing treatment is shown, and FIG. 5 is a step-by-step cross-sectional view of a conventional positive photoresist pattern forming method. In the figure, 1 processed group & 2 positive type photoresist films, 2a the exposed part of #-1 resist, 2b the unexposed part of the Vi resist, 2c the uncured part of the resist, 2d
3 is the chrome pattern part of the mask pattern, 4 is the empty pattern part in the mask pattern, 5 is the photosensitive light of the resist, 6 is ultraviolet light, 7 is substrate heating, 8#: l: heat 9 is heating. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] (1)被加工基板上に所定のポジレジストパターンを形
成する方法において、レジストパターン内に、レジスト
パターンの厚み以下の深さの溝を入れることを特徴とす
るレジストパターン形成方法。
(1) A resist pattern forming method for forming a predetermined positive resist pattern on a substrate to be processed, the method comprising forming a groove in the resist pattern with a depth equal to or less than the thickness of the resist pattern.
(2)前記、溝の作成を転写するマスクの個々のパター
ン内部に空きパターンを付加するようにことを特徴とす
る特許請求の範囲第1項記載のレジストパターン形成方
法。
(2) A resist pattern forming method according to claim 1, characterized in that an empty pattern is added inside each pattern of the mask to which the groove formation is to be transferred.
JP13425387A 1987-05-27 1987-05-27 Formation of resist pattern Pending JPS63296221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13425387A JPS63296221A (en) 1987-05-27 1987-05-27 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13425387A JPS63296221A (en) 1987-05-27 1987-05-27 Formation of resist pattern

Publications (1)

Publication Number Publication Date
JPS63296221A true JPS63296221A (en) 1988-12-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP13425387A Pending JPS63296221A (en) 1987-05-27 1987-05-27 Formation of resist pattern

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541352A (en) * 1991-08-06 1993-02-19 Nec Kyushu Ltd Manufacture of semiconductor device
JP2009027062A (en) * 2007-07-23 2009-02-05 Nec Electronics Corp Method of manufacturing semiconductor device
JP2009027060A (en) * 2007-07-23 2009-02-05 Nec Electronics Corp Method of manufacturing semiconductor device
US8137898B2 (en) 2007-07-23 2012-03-20 Renesas Electronics Corporation Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541352A (en) * 1991-08-06 1993-02-19 Nec Kyushu Ltd Manufacture of semiconductor device
JP2009027062A (en) * 2007-07-23 2009-02-05 Nec Electronics Corp Method of manufacturing semiconductor device
JP2009027060A (en) * 2007-07-23 2009-02-05 Nec Electronics Corp Method of manufacturing semiconductor device
US8137898B2 (en) 2007-07-23 2012-03-20 Renesas Electronics Corporation Method for manufacturing semiconductor device

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