JPS63292487A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To execute a test of plural memory cells and a test of every 1 bit by a read-out operation of once, by comparing successively the contents of a write use shift register and a read-out use shift register. CONSTITUTION:At the time of a test, a data of N bits outputted from a test data generating circuit 33 is stored in a write use shift register 36, the data of the register 36 is written in parallel by N bits in a memory cell 1 of N bits selected by an address outputted from an address generating circuit 29, and this written data is read out and stored in a read-out use shift register 42. Subsequently, from the register 36 and 42, the corresponding data are outputted successively, and compared by a logic circuit 52. As a result, a test of plural memory cells is executed by a write/read-out operation of once, and also, a test of every 1 bit can be executed.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor memory device.

Conventional technology Conventional semiconductor memory is used for functional testing.

The method is to sequentially input all addresses corresponding to all memory cells from the address bin and write or read arbitrary data from the data pins.The method to shorten test time is to use normal readout, which reads each bit one by one. In addition to this method, a method is used in which the match or mismatch of data stored in a plurality of bits of memory cells read internally is outputted to the outside, and a function test of a plurality of memory cells is performed simultaneously.

Problems to be Solved by the Invention However, in the test function of such a semiconductor memory device, it is necessary to input addresses sequentially from the outside.
Test time will increase. Also.

In this method, if it is necessary to know the address of a defective memory cell, the multiple memory cells that are being tested at the same time must be read out one pit at a time using normal reading means, so testing is performed at the same time to shorten the test time. As the number of memory cells increases, the time required to determine the address of a defective memory cell increases.

The present invention solves these conventional problems and makes it possible to test a plurality of memory cells in one read operation and to test each bit individually.

Means for Solving the Problems The semiconductor memory device of the present invention includes a test data generation circuit that generates and outputs N-bit data, and stores and outputs the N-bit data output from the test data generation circuit in parallel. a shift register for writing into an N-bit memory cell; a read shift register for storing N-bit data read from the N-bit memory cell in parallel and sequentially outputting it one bit at a time; and the grouping register. and a logic circuit that compares the 2-bit data sequentially output from the read register to detect a match or mismatch, and an address generation circuit that generates an address for selecting the N-bit memory cell. It is.

Operation During a test, the semiconductor memory device of the present invention stores N-bit data output from the test data generation circuit in a write shift register, and stores N-bit memory cells selected by the address output from the address generation circuit. The data in the write shift register is written in N bits in parallel, and the data written in the N bits of memory cells is read out and stored in the read shift register.

Next, by sequentially outputting the corresponding data from the write shift register and the read shift register and comparing them using a logic circuit, multiple memory cells can be tested in one write/read operation, and each memory cell can be tested bit by bit. testing becomes possible.

Example Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, a memory cell array T1 has a plurality of memory cells arranged in a matrix.Here, to simplify the explanation, 16-pit memory cells 2 to 17 are arranged in a 4×4 matrix. Four bit lines 18 to 21 are provided in the horizontal direction, and four word lines 22 to 26 are provided in the vertical direction. External address input terminals 27 and 28 and address generation circuit 2
The output of 9 is input to multiplexer 3o.

The output of the multiplexer 3o is input to the row decoder 2e, and the row decoder 26 outputs the four word lines 2.
Select one from 2 to 25. When the address switching signal 32 output from the test control circuit 32 is 1, the multiplexer 3o selects the external address input terminal 27.2.
8, and when the address switching signal 31 is 0, the output of the address generation circuit 29 is output. row decoder 26
teeth.

The upper bit of the input address is 0. lower bit is 0
When the word line 2'2'i, the upper bit is 0°, the lower bit is 1, the word line 23 is connected, and the upper bit is 1. When the lower bit is 0, the word line 24 is selected, and when both the upper and lower bits are 1, the word line 26 is selected. The lower bits of the address output from the address generation circuit 29 are also input to the test data generation circuit 33. The output of the test data generation circuit 33 is initialized to the value of the lower address from the address generation circuit 33 when the test data reset signal 34 becomes 1, and outputs 0 and 1 alternately every time the clock 36 falls. Test data generation circuit 33
The output of is input to the write shift register 36,
Data is shifted every time the clock 35 falls. The parallel outputs of the write shift register 36 are connected to the bit lines 18 to 21 by write switching transistors 39 to 4o, and the write switching transistors 37 to 40 receive the write signal 41.
controlled by. Read shift register 4
2 are connected to the bit lines by read transistors 43 to 4θ, and read transistors 43 to 46 are controlled by a read signal 4. The read sister register 42 stores data from the read transistors 43 to 46 when the load signal 48 is 1, and performs a shift operation every falling edge of the clock 36 when the load signal 48 is 0. The serial output of the write shift register 36 and the serial output of the read shift register 42 are input to the logic circuit 52, and when these two data match, 0 is sent to the external output terminal 63, and when they do not match, 1 is sent to the external output terminal 63. Output. FIG. 2 shows an example of the logic circuit 62. Input terminal 55. If the inputs of E56 match, 0 is output to the output terminal 63, and if they do not match, 1 is output.

Next, an outline of the operation of the embodiment of the present invention shown in FIG. 1 will be explained.

When the input from the test mode switching signal input terminal 49 is 1, the address switching signal 31 is 1, and the row decoder
Inputs from external address input terminals 27 and 28 are input. Further, when the address reset signal 60 is 1, both bits of the output of the address generation circuit 29 are 0.

The test data reset signal 34 is also set to 1.

First, a write operation is performed. When the input from the external write signal input terminal 64 is 0 and the input from the test mode switching signal input terminal 49 becomes 0, the address switching signal 31 becomes 0 and the output of the multiplexer 30 is switched to the output of the address generation circuit 29. Alternatively, word line 22 is selected first. Further, the address reset signal 50 and the test data reset signal 34 also become 0. Since the lower bit of the output of the address generation circuit 29 is 0, the test data generation circuit is outputting 0. Next, when the clock 36 rises and falls once, the first bit of the write shift register becomes 0.
Therefore, the output of the test data generation circuit 33 becomes 1. Furthermore, when the clock 35 rises and falls once, the 2nd bit of the write shift register 3600 becomes 1, and the 0.1 bit becomes 1, and the output of the test data generation circuit 33 becomes 0. When the clock 35 repeats rising and falling four times.

The output of the write shift register 36 becomes 01o1. Next, the write signal 41 becomes 1, and the parallel output of the write shift register 36 passes through the write switching transistors 37 to 4o to the bit lines 18 to 2.
1 and written into the memory cells 2 to 6 selected by the word line 22. Next, a pulse is output to the address clock 51, and the output of the address generation circuit becomes 0 for the upper part and 1 for the lower part, and the test data reset signal 3
4 becomes 1 for a certain period of time, and the test data generation circuit 33
The output of becomes 1. Subsequently, when the clock 36 repeats rising and falling four times, the output of the write shift register 38 becomes 1010. When the write signal 41 becomes 1, this output is.

Written to memory cells 6 to 9. By repeating this process and writing to all memory cells, a checkerboard pattern as shown in FIG. 3 will be written to memory cells 2 to 17.

Next, a read operation is performed. If 0 is input from the test mode switching signal input terminal 49 while 1 is input from the external write signal input terminal 54, the word line 22 is selected first, and the data 0101 is input to the write shift register 36, just as in the write operation. is written. Next, when the read signal 47 is set to 1, the data stored in the memory cells 2 to 6 is input to the read shift register 42 through the read transistors 43 to 4e. Then, the load signal 48 is turned off for a certain period of time, and the data is stored in the read shift register 42. After that, the serial outputs of the write shift register 36 and the read shift register 42 are input to the logic circuit 52 every time a pulse is input to the clock 48 . If the memory cell corresponding to the output is functioning normally, the output of the write shift register 36 and the output of the read shift register 42 should match, and the external output terminal 6
3 is output as 0. If the memory cell is not functioning normally, the output of the write shift register 36 and the read shift register 42 will not match, and 1 will be output to the external output terminal 63, indicating that the corresponding memory cell is defective. I understand that there is something. By repeating this and reading out all the memory cells, it is possible to perform a functional test on all the memory cells 2 to 17.

As described above, 4 bits of data is input into the write shift register once, written to 4 bits of memory cells at once, and 4 bits of data are read out in one read operation for comparison, which significantly reduces test time. Can be shortened. Further, since the test is performed on a bit-by-bit basis rather than based on matching or mismatching of a plurality of bits, a checkerboard pattern test can be easily performed, and the address of a defective memory cell can also be easily determined.

Effects of the Invention As described above, according to the present invention, one write operation can simultaneously write to multiple memory cells, and one read operation can read from multiple memory cells. Significant time savings can be achieved, and it is only necessary to look at the output of one bit. Furthermore, 1
Since the test is performed for each memory cell, it is easy to determine the address of a defective cell, and since there is no need to write the same data to a plurality of memory cells, testing using a check board pattern or the like is also easy.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a logic circuit constituting the device, and FIG. 3 is a block diagram of a semiconductor memory device according to an embodiment of the present invention. FIG. 3 is an explanatory diagram of a checkerboard pattern. 33...Test data generation circuit, 36...
...Writing shift register, 42...Reading shift register, 52...Logic circuit, 2
9...Address generation circuit, 32...Test control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figures s, t: Figure 3

Claims (1)

[Claims] a test data generation circuit that generates and outputs N-bit data; a write shift register that stores the N-bit test data output from the test data generation circuit, outputs it in parallel, and writes it into the N-bit memory cell; N
Compare the read shift register that stores N-bit data read from the bit memory cell in parallel and sequentially outputs it one bit at a time, and the 2-bit data sequentially output from the write register and the read shift register. A semiconductor memory device comprising: a logic circuit for detecting match or mismatch; and an address generation circuit for generating an address for selecting the N-bit memory cell.