JPS63291108A - Processor - Google Patents

Abstract

PURPOSE:To process a complicated arithmetic operation, as well at high speed with a simple constitution by using all inputs and data, etc., to be processed as the input address of an exclusive ROM for operating and using the output of the ROM as an arithmetic result. CONSTITUTION:When an adding instruction between resistors are decoded by an instruction decoding part 10, a ROM 1 for adding is made active by the instruction decoding part 10 and simultaneously to the address part of an access bus 100, in order to output the contents of the respective resistors to be added, a signal is sent from the instruction decoding part 10 to a resistor group and control part 20. As a result, the ROM 1 for adding outputs an added result to the access bus 100, the resistor group and control part 20 inputs it from the access bus 100 and stores it to the designated resistor of the internal part of the resistor group and control part 20 and a solution is obtained. Thus, a complicated arithmetic processing can be executed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a computer processing system, and particularly to a high-speed processor.

Conventional technology Conventionally, in this type of sequential processor, in order to decode an instruction after fetching it and perform the necessary processing,
Data was input to arithmetic circuits such as adders, shifters, multipliers, and dividers, and the output was obtained.

Problems to be Solved by the Invention: In the conventional processor processing method described above, data is input to an arithmetic circuit and its output is obtained, so it has the disadvantage of being slow.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to provide a novel processor that is capable of executing complex arithmetic processing at high speed. It is in.

Means for Solving the Problems In order to achieve the above object, the processor according to the present invention comprises:
Equipped with (a) various ROMs that store all operation results in advance, and (b) a control circuit that decodes instructions and determines which ROM and register to select from among the various ROMs. It is composed of

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. ■ is a ROM for addition, 2 is a ROM for subtraction,! 1 represents other calculation P and OM. The outputs of these ROMs are output to a ROM access bus 100. ! 0 is an instruction decoding unit which receives an instruction from the bus interface unit 30, decodes the instruction, and instructs the 20 l/gis 9 groups and the control unit as to the type of register and input/output, and at the same time If necessary, one of the calculation ROMs 1 to n is selected and made active. When the bus interface unit 3θ receives a bus access request from the register group and the control unit 20, it outputs information to and from the main memory or various Ilo via the 7-stem bus 200.

As an example of operation, an addition instruction between registers is executed by the instruction decoder 10.
, the instruction decoder 10 activates the addition ROMI, and at the same time the access bus 1
In order to output the contents of each register to be added to the address section 00, a signal is issued from the instruction decoding section 1O to the register group and the control section 20. As a result, the addition RO
The MI outputs the addition result to the access bus 100, and the register group and control section 20 inputs it from the access bus 100 and stores it in a designated register inside the register group and control section 20 to obtain an answer.

As described in detail, according to the present invention, all inputs, data, etc. to be processed are used as input addresses of a dedicated ROM for calculations, and the output of the ROM is used as the calculation result, so that rrr+ 'J-like configuration provides the advantage of being able to process any complex calculations at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 109. Addition ROM, 2. ,, ROM for subtraction. n90. Representatives of other calculation ROMs, 10. ,,instruction decoding unit, 20. , , register group and control unit, 30.
,. Bus interface section, +00. ,,ROM access bus, 200. ,, system bus

Claims (1)

[Claims] In a computer processing method, all inputs, data, etc. to be processed are used as input addresses of a dedicated ROM (read-only memory) for calculations, the output of the ROM is used as the calculation result, and data processing and control are performed by the ROM. A processor characterized by using output.