JPS63290979A - Superconducting quantum interference device - Google Patents

Abstract

PURPOSE:To enable processing and feeding back by a superconducting circuit so that an element can be formed to one chip by adding a pulse and triangular or saw wave to a bias and magnetic field coupling line and taking out the value of a magnetic flux or the current to be measured as a pulse wave. CONSTITUTION:A Josephson junction attains a voltage state when a bias current exceeds a threshold value. This threshold value changes with a signal current. The voltage state is attained even if the bias current IB is small if the signal current IX+IC is large in positive and negative directions. The right side of a straight line D is the voltage state when there is the bias pulse and is the non-voltage state if there is no pulse if the amplitude of IB is previously so selected as shown in the figure with respect to a threshold characteristic C. The pulse voltage V similar to the bias pulse is then obtd. from an output terminal out. The left side of the straight line D is the non-voltage state regardless of the presence or absence of the bias pulse and no pulse voltage appears in the output out.

Description

[Detailed Description of the Invention] [Summary] A pulse and a triangular wave or wave control are applied to the bias and magnetic field coupling line of 5QIIID, and the value of the magnetic flux or current to be measured is extracted as the number of pulses. Processing and feedback using superconducting circuits are now possible, making it possible to integrate into one chip.

[Industrial application field]

The present invention provides current or magnetic flux that can be converted into current, voltage,
This invention relates to superconducting quantum interference devices (referred to as SQUIDs) used to measure resistance and the like.

[Conventional technology]

3 ports [lID is a highly sensitive detector, especially 5QUID
Magnetometers are more sensitive than all other magnetometers. A conventional magnetometer called DC5 (ltllD) is shown in Figure 15. (a) is a two-junction superconducting quantum interference device (DC5QUID).
), Jl and J2 are Josephson junctions, and β1 is a circuit that supplies bias current I to the superconducting loop including Jl and J2. β2 is a signal line through which a signal current lx flows, and in the case of a magnetometer, this current lx is supplied by a pink amplifier coil interlinked with the magnetic flux to be measured. The superconducting loop including the junctions Jl and J2 and the signal line 7!2 are coupled by a mutual inductance M. Josephson junction J1. For J2, either a bridge junction that inherently has no hysteresis in the IV characteristics, or a L-channel type junction that has hysteresis in the ■-■ characteristics and connects a resistor in parallel to eliminate hysteresis (the example shown is ) is often used. The I-■ characteristics are shown in Figure 15 (bl) (where curve C1 is MI x = n-1, curve C2 is MI
This is the case of x-(n+-)φ0.

A superconducting circuit is dominated by inductance, which is represented by a coil symbol in Tal as shown in the figure. When bias current I is applied, junction J! If the inductance is the same on the J2 side and the J2 side, 1/2 will flow to each side. When this current summer/2 is below a critical value, the Josephson junction is in a no-voltage state, and the voltage V at the output terminal Out is zero. The critical value varies depending on the signal current Ix, and if Ix=0, it is Ico. As Ix gradually increases from 0, the critical value 1c gradually decreases and becomes Ic+ at MIx-φo/2. lx
As becomes even larger, the critical value begins to rise and becomes Ico at Mlx-φ0. When it gets even bigger, it starts to go down again, and the same changes repeat thereafter. In the end, M T x = n-1 (n=
0.1.2. ), Ic=Ico, MIx
= (n+1) I c = Ic1 at φ0, and changes periodically during this period. Here, φ0 is a magnetic flux quantum,
n=0 is called O mode, n=1 is called 1 mode, etc., and φ0 is 0. 1. 2. ...
...Indicates the entered state. When the bias current flowing through a Josephson junction exceeds a critical value, the junction enters a voltage state, and the voltage Ix increases according to r along curves CI, C2, or an intermediate curve (not shown). increase The relationship between MIx and V is as shown in FIG. 15 (c+), showing periodic changes.

In FIG. 15 (C1, MIx = 0 and V has a value V1 that is not O, so I exceeds Ic (IB of bl). In this state, when lx is increased, the curve falls. te■ becomes large, reaches its maximum at C2, and from then on the curve becomes
2 and V is lowered (C1 indicates this repetition).

lx is the signal current, and if it is a magnetometer, it is the change in the magnetic flux linked to the pink amplifier coil.If you know V from fc), you can find Ix, so in the end, you can measure the voltage V at the output terminal Out in the fa1 diagram, and if it is a magnetometer, You can know the magnetic flux interlinking with the pickup coil.

However, as shown in Fig. 15 fcl, ■ changes periodically, so even if a certain value V3 is obtained, Mlx
I don't know if it's MIx+ or MIX2. In addition, there are problems such as the drift of the bias current source and the DC amplifier that measures the output voltage (■) affecting the output, so the actual measurement circuit is as shown in Figure 16.
The feedback current is passed so that the operating point is always the minimum point of the V-MIx characteristic.

In this FIG. 16, the PC is the pink amplifier coil described above, and no signal current rxo flows through the signal line 12. β3 is the feedback current If
In this circuit, the sum of these currents I xo
+I f becomes the signal current lx in FIG. IB in (b) is used as the bias current I, and therefore the V-Ix characteristic becomes as shown in FIG. .

A2 is an amplifier, and AI amplifies the voltage V at the output terminal Out and applies it to the lock-in amplifier A3. Lock-in amplifier A
3 generates a direct current output according to the amplitude and phase of the same frequency component as the reference signal Ref in the input voltage (product output; if in phase, +■1°; if out of phase, -v2.1/4 period shift. If O), the amplifier A2 amplifies this and outputs it to the signal line 113 through the resistor RF. The output of the oscillator O8C is connected to the signal line I! via the capacitor C. Therefore, the feedback current If has the form To+ksinωt.

Since the signal current has a sinωt component of the oscillator OSC, the output voltage V also has a sinωt component.

Lock-in amplifier A3 outputs a positive voltage if it is in phase, and a negative voltage if it is out of phase. This increases or decreases the output IO of A2, and eventually the operating point is changed to Fig. 15 (Min of C1).
Set to the minimum voltage point shown by . This can be easily explained as follows. That is, when the current 0 supplied from the amplifier A2 is rol, If becomes If of tc+ in FIG. 15, and when it increases, V decreases, and this is reversed by A+ to increase and become in phase with Ref. Therefore, lock-in amplifier A
The output of 3 is positive and Iol increases. Also ■0 is IO2
When If becomes If2 in Fig. 15 (cl), when it increases, ■ increases, is inverted by AI and decreases, and becomes in opposite phase to Ref. Therefore, the output of A3 becomes negative, Io2 decreases, In this way, we finally settled on the Min point (.

Let this circuit settle at the Min point with a signal current of 1 xo=Ioo
The signal current 1xo is determined as -Io.

[Problem that the invention seeks to solve]

As shown in Figure 16, the conventional 5QUID has an analog output V, and requires analog circuits such as low-noise amplifiers AI, A2, and lock-in amplifier A3 to determine the operating point using the analog voltage V. shall be. Since these normally operate at room temperature, they have higher thermal noise than the old SQ elements that operate at liquid helium temperatures, causing a decrease in sensitivity.

There are examples of using GaAs FETs that operate at liquid helium temperatures as the first stage booster, but since the manufacturing process is different from the old SO gate, which is made of Josephson junctions, it is easy to create an integrated circuit that integrates these. Not.

The present invention also enables the attached circuit to be fabricated using a superconducting circuit including a Josephson junction, and to construct the 5QU on the same chip.
This is intended to provide an ID.

[Means for solving problems]

In the present invention, the bias of the 5QUID is applied in the form of a pulse so that the output becomes a pulse (digital) so that it can be easily handled by a superconducting circuit including a Josephson junction. The principle diagram is shown in Fig. 1.

The equivalent circuit of Fig. 1 is shown in Fig. 15 (not much different from al.
The bias current is a pulse current IB(t) as shown in the figure,
The signal line! 42. ! ! The current to be measured lx is applied to I12 as a.
is applied, and a triangular wave current of 1cltl is applied to β4.

A pulse voltage appears at the output terminal Out, and is counted by the counter CTR. Josephson junction J1 in this circuit
．． J2 is shown in Fig. 15 (unlike al, it is desirable that it has hysteresis. The frequency fc of the triangular wave current 1cftl is made sufficiently smaller than the frequency fB of the bias pulse current IB(t). Fig. 2 shows the dark value characteristic. and the operating point.

[Effect]

When the bias current exceeds the dark value, the Josephson junction enters a voltage state, but this dark value varies depending on the signal current. In FIG. 1, the signal current is Ix+Ic, and when this becomes large in the positive and negative directions, the bias current IB becomes a voltage state even if it is small. Curve C indicates the boundary between a voltage/no-voltage state; above curve C is a voltage state, and below curve C is a no-voltage state. If the amplitude of the bias current IB is selected for the dark value characteristic C as shown in the figure, on the right side of the straight line (Ic+Ix is 1th
(If above) When there is a bias pulse, there is a voltage state, when there is no voltage, there is no voltage, and from the output &10ut a pulse voltage V similar to the bias pulse is obtained, and on the left side of the straight line (when Ic + Ix is less than I th) the bias pulse No pulse voltage appears at the output terminal Out in a no-voltage state regardless of the presence or absence of the output terminal Out.

The period T during which the pulse voltage appears at the output terminal Out is Ic(
If the amplitude of O is Ico, the number m of pulse voltages appearing during this period T is m=rB-'
r, therefore. Since fB, fc, Ico, and 1th are known, by measuring m, the current to be measured lx can be found. The number of pulses m can be counted by a counter, and a digital element such as a counter can be easily constructed using a superconducting circuit including a Josephson junction. Therefore, it is possible to easily incorporate an auxiliary circuit into the same chip as the IUID.

(Modification) The dark value characteristic may be made asymmetrical, or a portion of the bias current may be shunted and passed through the signal line, and the same operation can be obtained even in this case. The bias pulse wave IBftl is not limited to a rectangular wave, and both IB(tl and IC(tl) may have an offset. The control current 1c(t) has a dark value, and the bias pulse IB(t) has a constant peak value.
It can be said that it searches for a point that exceeds the darkness value at 11. Therefore, if it has a gradually increasing portion, it is not limited to a triangular wave, but may also be a sawtooth wave, a trapezoidal wave, etc. If the nonlinearity is known, the current to be measured can be calculated from the output count number m.

FIG. 3 shows an example in which both IBltl and Ic(t) have positive and negative symmetrical waveforms, and the dark value characteristics are asymmetrical. The dark value characteristic C of this example is Josephson junction J1. The ratio of each critical current of J2 is obtained by setting it to 1'1:3. In general, various types of dark value characteristics C can be obtained by changing this ratio, the value of the loop inductance, and the point at which bias current is injected into the loop. Further, in this example, the bias current IBitl is not a rectangular wave, but is stepped as shown in the figure to shorten the time it takes to reach the peak value. In this way, malfunctions due to thermal noise, etc. that may occur when the operating point approaches the dark value are less likely to occur.

Also in FIG. 3, a pulse is generated at the output terminal Out at the point where Ic (tl+Ix) exceeds the point 1th where the peak level of IB intersects with the dark value characteristic C, and lx is found by counting the number mI and m2. That is, Ic(tl + T
On the positive side of x, holds true, and therefore Ic (on the negative side of tl+Ix, lx becomes from these f21. There are advantages.

Although the number of pulses m, ffl1, and m2 are several in FIGS. 2 and 3, they are actually set to a large number, such as 100, to improve accuracy.

The reason why the dark value characteristic is made asymmetric in FIG. 3 is so that only the output due to the positive wave of the bias pulse appears on the right side of the dark value characteristic, and only the output due to the negative wave appears on the left side of the dark value characteristic. If it is made symmetrical, positive and negative waves will appear on the left and right sides, respectively, and you will have to deal with them, which is troublesome.

〔Example〕

Figure 4 shows the circuit configuration of a magnetic flux needle equipped with a feedback circuit consisting of a superconducting circuit. 10 is an oscillator that generates a sine wave of frequency fB, and 12 is a JJ pulser that converts the sine wave of frequency 1B into a pulse (pulse with a short peak period) of the same frequency and the illustrated waveform, and converts this into a bias pulse r B (as tl). 5QUID.Output frequency f of oscillator 10
B is frequency-divided by a frequency divider 14, passed through a low-pass filter LPF to form a triangular wave 1c(t) with a frequency fc, and is supplied to the signal line β4. In addition, the output pulse of the output terminal Out is supplied to the up/down counter CTR, and the polarity detection circuit 18 discriminates between positive and negative waves, and the counter CTR is sent to the counter CTR for up/down l-u when the wave is positive, and down-down l-u when the wave is negative. -d.

Therefore, the count value of the counter CTR is the aforementioned ml-m2, which becomes the output of the magnetometer circuit. This output is also applied to the PID control circuit 22 to become the P (proportional) component, D (differential) component, and ■ (integral) component of feedback control, and the sum of these is D/A converted by the converter 24. It is added to the signal line 7!3 as a feedback current If to perform control to bring the output voltage ■ described in FIG. 15 to the minimum point old n.

This 5QUID magnetometer in Figure 4 also has a counter CTR1PI.
Although additional circuits such as the D control circuit 22 are required, these can be constructed from superconducting circuits, etc., and can be integrated into a single chip with the 5QUID main body. Next, an example of the configuration of each part is shown.

Examples of the configuration of the amplifier down counter CTR are shown in FIGS. 5 and 6. As shown in Fig. 5, the counter CTR is formed by cascading the required number of stages of circuits CL C2... with the same configuration, and the first stage C1 receives the clocks CK and CK as input, and receives the counted value. Outputs the first bit (LSB) A+. The second stage C2 receives the carry of C1 and outputs the second via l□A2.

The same applies below. FIG. 6 shows the circuit configuration for one stage.

Figure 6 shows one stage of the dual-rail counter.
It is composed of a latch circuit 30, and a logic circuit including an OR gate Ga1 indicated by a cross, and an ant gate Ga1 Gb+ indicated by a . In the case of first stage C1, inputs Xn-1, Xn-
1 is the clock CK, GK, and the output An of this stage is A1. Output Xn to the next stage, Xn is Xn=X, 1-
+ (An, u+A1.d), Xn-Xn-+ +
An, d+An, u. When counting amps, u=
1. d=0, and when counting down, d=1. u=
becomes 0.

FIG. 7 shows an example of the launch circuit 30. There are various types of U-nochi circuits, but this one uses three-phase power supplies #1, #2. #
3 and 3 OR gates Ga and timed inverter T
A circuit consisting of 1 is used. The output of AND gate Gb2 is set to 3-phase power supply #1. #2. It is sequentially taken into each OR gate at phase #3, and output An is produced after a delay of 2π/3. The output An is from the second OR gate to the timed inharter T.
It is output through I. A Josephson junction with hysteresis enters a voltage state when the bias current exceeds the dark value, and this voltage state is maintained until the bias current reaches zero. Each OR gate Ga of the launch circuit 30 operates as described above. When the input is 1 and the #1 power supply is turned on, the first OR gate becomes a voltage state (latches) when the threshold value is exceeded, and the #1 power supply is turned on. This state is maintained until it reaches 0.

The second and third OR gates operate in the same manner. The timed-in-hark TI is essentially an inverter that produces an output An that is opposite to the output An of the No. 3 OR gate, but since it is difficult to produce the first inverted output with an inverter using a Josephson junction, a special addition is required for this purpose. It has a circuit. Two types of circuits are known for this purpose, and any of them may be used.

The operation of the circuit shown in FIG. 6 will be explained for the case of up-counting and for the first stage CI. In this case, the output Xn is
I-IAn Therefore CK-A1, Xn is X rl-H+
An is therefore CK+AI. Before the first clock enters, Xn-+ =0+ Xn-r =1. An-〇, Xn=0. Xn=1.

When the first clock enters, Xn-+ = 1+ Xn-+
=0, and since An=0 at the time of this first clock input, the output of AND gate Gb2 (A n +Xr)-1
) (Ω+X r+-+) is 1, this is lunch 30
An=1 after the delay. Note that the OR gate Ga2 and the like operate with the #1 power supply. Also, since An=0 at the time of the first clock input, the first stage output X+ is 0,
Xl is 1.

When the second clock is input, since An=1, the output of the AND gate Gb2 becomes O, which is taken into the launch 30, and after the delay, An=0. Also, since An=1 at the time of inputting the second clock, the output X1 is 1,
It becomes l-0.

When the third clock is input, since An=0, the output of the AND gate Gb2 is 1, which is taken into the latch 30, and after the delay, An=1. Output X1 is O,,xl
is 1.

Similarly, the output An of the first stage is 0, 1, 0, 1°...
...and the carry output Xn to the next stage is 0.0゜1
．． It becomes 0.1... The second stage C2 counts this carry output Xn and sets A2 to 0. 0. 1. 1.
0°0, . . . and a carry output is generated to the next stage. The operations of the other stages C3, C4, . . . are similar. When counting down, u=o and d=1, so the borrow output to the next stage is Xn=X11-1 ・An+
Xn=Xn-1+An.

As described in the specification of a separate application, the JJ Pulsar 12 has one Josephson junction and a resistor connected in series, a two-open series Josephson junction connected in parallel to these, and a sine wave applied to these. /J can be generated by a circuit whose output terminal is a series connection point.

FIG. 8 shows an example of the D/A converter 24. The main body is the well-known R
Although it is a -2R ladder type circuit, the current supplied to each note is controlled by an OR game LG a using a Josephson element. AI, A2. . . . An is each bit of the digital input. When An is 0, the gate is in a no-voltage state, and all bias current IB flows through the gate and is dropped to ground. If 80 is 1, the gate is in a voltage state, and the bias current IB also flows to the node Nn. The same applies to gates of other bits. Each node is connected to ground through three 2Rs, and if IB is supplied to each node, IB/3 flows to each 2R. Therefore, when A'n = 1, the output line 7!5 flows to the Nn side, and I s / 3 (7) 1 / 2 becomes 7!5.
2 current, and the following applies accordingly, so the current I flowing through the output line β5 is as follows (5). This is nothing but a D/A conversion output of an n-bit binary number with A1 as LSBXAn as MSB.

These resistors can be replaced with superconducting inductances L, 2L as shown in FIG. The current flowing through the output line 15 is also expressed by equation (5).

Further, as shown in FIG. 10, a mutual inductance M may be used. In this case, the current I flowing through the output line 7!5 is (6). PTD control can also be performed on the analog quantity of the D/A conversion converter, but as shown in FIG. Weighting can be performed by a combination of circuits 42.

In other words, the proportional (P) component is the output of the register 32 as it is\,
The differential (D) component is obtained by calculating the difference from the previous value in the register 34 with a subtracter 38, and the integral (1) component is weighted by adding the previous sum of the register 36 to the current value in an adder 40. is input to the adder 42, the output of the adder 42 becomes the PID control output. These adders and subtracters can be realized using Josephson logic circuits and can be integrated into one chip.

The frequency divider 14 for creating a triangular wave of frequency fc may use the amplifier down counter CTR with u=l and d=0. Of course, u=1. Since d-〇, FIG. 6 can be simplified as shown in FIG. 13. Figure 12 shows N stages of counter stages C1, C2, .
This shows the state in which ri is obtained. Figure 13 shows the first stage of the counter, where the inputs X1-1 are CK-AI-A2...
・A1-1, Xi-1 is GK+A+→-A2+...
...A1-1, output Xi to the next stage is CK-A1/A2
・・・・・・Ai, Xi are CK+A11-A2+...
...Ai. Output of AND gate Gb? t (
A i +X4-+ ) (A i +X+-1)
= At■X1 heat (here ■ is EOR).

The low-pass filter LPF can be constructed from a circuit consisting of a superconducting transformer TR, a resistor R, and an inductance L, as shown in FIG. In this circuit, if the time constant of RL is made sufficiently large, when a rectangular wave enters the input terminal IN, the output line β6
A triangular wave current flows through.

Although each circuit in FIGS. 4 to 14 is realized by a superconducting circuit, other circuits that perform similar functions may be used as long as they can be integrated into a single chip with 5QUID. Alternatively, the feedback circuit in FIG. 4 may be removed and the current to be measured lx may be obtained from the difference in the number of pulses. Triangular wave or sawtooth 1 with frequency fc
c(t) may be generated separately (asynchronously) without using the same oscillator output as I B (t). The output of the counter CTR shown in FIG. 4 may be further stored and processed by a superconducting circuit or the like, and it is also possible to convert it into D/Af and output it.

〔Effect of the invention〕

As explained above, in the present invention, since the output of the 5QUID is extracted as a number of pulses, it can be processed by a superconducting circuit consisting of a Josephson element etc. that is good at digital processing, and a feedback circuit etc. can be configured. It becomes possible to integrate on the same chip using the same process, and it is possible to provide a small and highly sensitive 5QUID.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle of the present invention, Figs. 2 and 3 are explanatory diagrams of the operation of Fig. 1, Fig. 4 is a block diagram showing an embodiment of the invention, and Fig. 5 is a block diagram of an amplifier down counter. , Figure 6 is a circuit diagram for one stage of counter, Figure 7 is a launch circuit diagram and waveform diagram, Figures 8 to 10 are D/A converter circuit diagrams, and Figure 11 is a PID control circuit diagram. Block diagram, Fig. 12 is a block diagram of the frequency divider, Fig. 13 is a circuit diagram of one stage of the frequency divider, Fig. 14 is a circuit diagram of the LPF, Fig. 15 is an explanatory diagram of the conventional 5QtllD, FIG. 16 is a circuit diagram of a conventional magnetic flux needle. In FIG. 1, Jl and J2 are Josephson junctions, fBftl is a bias current, lx is a current to be measured, re(tl is a control current, Out is an output terminal, and CTR is a counter.

Claims (3)

[Claims] (1) In a superconducting quantum interference device consisting of two or more Josephson junctions (J_1, J_2) and a superconducting loop, a current waveform (I_B(
t), I_C(t)), and means (CTR) for counting the number of output pulses of the superconducting quantum interference device. (2) A superconducting quantum interference device according to claim 1, wherein a part or all of the current waveform supply means and the output pulse counting means are constituted by a superconducting circuit. (3) The superconducting quantum interference device according to claim 1 or 2, wherein the current waveform supply means includes a feedback current supply means generated by the output of the output pulse counting means. .