JPS6328383B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal receiver for receiving and detecting PCM (Pulse Code Modulation) encoded signals consisting of one or more frequencies.

Conventionally, in analog multifrequency signal receivers,
By rectifying the filter output and inputting it to a signal detector and comparing it with its threshold level,
It was detecting a signal.

In this case, in order to prevent malfunctions due to excessive response of the filter when a signal arrives, the time point at which the signal arrives is detected, a guard timer is started from that point, and after the filter output reaches a steady state, the signal detection result is I was trying to output .

On the other hand, in conventional digital multifrequency signal receivers applied to discrete time systems (eg, digital communication systems), digital filters are usually used to perform frequency separation of signals.

However, when the signal frequency is relatively high and close to an integer fraction of the sampling frequency, the number of samples included in the same period of the digital filter is small, and the sampling point is almost the same over several periods. Sometimes.

Therefore, depending on the phase of the input signal, at the output of the digital filter, the sampling point may be near the maximum value of the input signal over several cycles, or the sample time may be relatively smaller than the maximum value over several cycles. There may be cases where the sample point is reached at different times.

In such cases, if the signal is detected using a digital detector that simply compares the output of the digital filter with a threshold level, even if the input condition is originally impressive, it may be difficult to detect the signal depending on the phase of the input signal. There were times when I was not impressed and could not obtain correct signal detection results.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to
An object of the present invention is to provide a digital signal receiver that can perform reliable signal detection.

The present invention is characterized by a maximum value holding circuit that can detect and hold the maximum value of the output of the digital filter corresponding to the input signal frequency at predetermined time intervals, and a maximum value holding circuit that can detect and hold the maximum value of the output of the digital filter corresponding to the input signal frequency, and a predetermined check function that detects each output from this circuit. The digital signal receiver further includes an output logic circuit capable of checking whether or not a correct detection result is obtained for a predetermined number of consecutive times, and outputting the detection result.

Embodiments of the present invention will be described below based on the drawings.

The figure is a block diagram of an embodiment of a digital signal receiver according to the present invention, which is for receiving and detecting a multi-frequency signal consisting of n frequencies.

Here, 1 is an input terminal, 2-1, 2-2,
..., 2-n are digital filters corresponding to each component frequency of the PCM encoded multi-frequency signal;
-1, 3-2, ..., 3-n are absolute value circuits that take the absolute value of the output amplitude value, 4-1, 4-2, ...,
4-n is a maximum value holding circuit that detects and holds the maximum value of the output at each predetermined time; 5-1, 5-2,
..., 5-n is a signal detection circuit that detects its output according to a predetermined threshold level, 6 is an output logic circuit, and 7 is a timer that performs timing control for each necessary circuit at each predetermined time. circuit,
8-1, 8-2,..., 8-n are output terminals.

First, a PCM encoded multi-frequency signal input from input terminal 1 is passed through digital filters 2-1 to 2-2.
Frequency separation is performed by n, and the outputs of the digital filters 2-1 to 2-n have their absolute values taken by the absolute value circuits 3-1 to 3-n, and then are sent to the maximum value holding circuit 4. -1 to 4-n.

Maximum value holding circuit 4-1 to which an absolute value signal is input
~4-n detects and holds the maximum amplitude value within a predetermined time T by timing control of the timer circuit 7;
The held value is sent to the corresponding signal detection circuits 5-1 to 5-n every predetermined time T.

Similarly, the signal detection circuits 5-1 to 5-n perform signal detection on the input holding value under timing control of the timer circuit 7, and send the detection results to the output logic circuit 6 at every predetermined time T. do.

Here, for each signal frequency to be received by this receiver, when the sine wave is sampled at the sampling frequency, the above-mentioned predetermined time T is calculated within that time by taking into account any phase difference between each sine wave and the sampling period. In this case, when the level difference between the maximum value of the sampling value and the peak value of the sine wave can be practically ignored and the input signal is significant, the maximum value of the sampling value is detected by the signal detection circuit 5-. 1 to 5-n and thereafter are determined so as to satisfy the reception standard. As a result, even when the signal frequency is close to an integer fraction of the sampling frequency, the disadvantages of the conventional example described above can be eliminated.

However, when the signal detection results are sent from the signal detection circuits 5-1 to 5-n, the output logic circuit 6
In order to prevent the receiver from malfunctioning due to the transient response of the digital filters 2-1 to 2-n or noise input, and to satisfy the time standard,
By checking the signal detection result a predetermined number of times m consecutively, its authenticity is confirmed, and only when it is determined to be true, the detection result is sent to the corresponding output terminal 8.
-1 to 8-n should be output. Note that even if it is not determined to be true, for example,
The data and information indicating the error may be output.

Here, in the above check, a reception code of n bits (equal to the number of signal frequencies constituting the multifrequency signal in the above embodiment) is created from the signal detection result, and the number of reception bits is determined according to the signal system. A predetermined check, e.g. 2 out of
Check n (only 2 out of n). In addition,
The signal is paused and terminated by checking 0 out of n.

Furthermore, the received code is created every time for the above-mentioned predetermined time T, and each time it is compared with the previous received code to check whether all bits match (all bit pattern match check). , during one signal reception period (for example, during reception of a signal for each digit of a multi-digit selection number), only those that have passed all bit pattern matching checks for a predetermined number of consecutive m times are written to the output memory; Output according to output order. Note that even if the test does not pass, the data and failure information can be output as described above.

The predetermined number of times m is determined, for example, so as to satisfy the following two conditions. That is, if the transient response time of digital filters 2-1 to 2-n at the time of signal input is Ts, and the momentary interruption guard time of the signal necessary for this receiver is T _G , then mT>Ts and mT>T _G. It is set to satisfy two conditions. This allows only significant signals to be detected and output.

In the above embodiment, maximum value holding circuits 4-1 to
4-n, output logic circuit 6, etc. do not require multipliers or the like specific to digital signal processing, and therefore can be realized with a relatively simple hardware configuration.

Further, the guard timer in the conventional example is not necessary because the timer circuit 7 and the output logic circuit 6 perform the same functions, resulting in cost savings.

It should be noted that the present invention is not limited to multi-frequency signals, but can obviously be implemented similarly to single-frequency signals.

As described in detail above, according to the present invention, it is possible to always perform reliable signal detection regardless of the frequency, phase, etc. of the input signal, and therefore it has a remarkable effect on improving the reliability of digital signal receivers. is obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a digital signal receiver according to the present invention. 1...Input terminal, 2-1 to 2-n...Digital filter, 3-1 to 3-n...Absolute value circuit, 4
-1 to 4-n...Maximum value holding circuit, 5-1 to 5-
n...signal detection circuit, 6...output logic circuit, 7...
...Timer circuit, 8-1 to 8-n...Output terminal.

Claims (1)

[Claims] 1 A digital device that has the function of receiving a PCM-encoded signal consisting of one or more frequencies, separating the frequencies with a digital filter, detecting the output with a signal detection circuit, and outputting the signal detection result. The signal receiver includes a maximum value holding circuit that can detect and hold the maximum value of the output of the digital filter corresponding to the input signal frequency at predetermined time intervals, and a predetermined check according to the detection of each output from this circuit. A digital signal receiver characterized in that it is configured to include an output logic circuit that is capable of detecting a correct detection result over a predetermined consecutive number of times, and outputting the detection result. vessel.