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JPS63283147A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63283147A
JPS63283147A JP62118261A JP11826187A JPS63283147A JP S63283147 A JPS63283147 A JP S63283147A JP 62118261 A JP62118261 A JP 62118261A JP 11826187 A JP11826187 A JP 11826187A JP S63283147 A JPS63283147 A JP S63283147A
Authority
JP
Japan
Prior art keywords
brazing material
hole
bonding
protrusion
supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62118261A
Other languages
Japanese (ja)
Inventor
Shoji Takano
高野 捷二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP62118261A priority Critical patent/JPS63283147A/en
Publication of JPS63283147A publication Critical patent/JPS63283147A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H10W72/536
    • H10W72/5363
    • H10W72/884

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To dispense with working of leads and supply of bonding material by a method wherein brazing material is applied to through-holes and peripheral parts. CONSTITUTION:A semiconductor element 6 is fixed to an insulating substrate 1 through a bonding agent 5 and connected electrically with a bonding wire 7, which is packaged with a resin mold 8. A spherical brazing material protrusion 9, which is formed in a soldering processing device such as a melting solder cell, is coated over a through-hole 3 and a rear land section 4. When the processing condition is kept constant, the protrusion 9 varies according to the diameter of the hole 3 and the area of the land section 4. The said brazing material 9 is used as bonding material when a mounting process is performed onto a printed substrate or the like. By these processes, when a mounting process is performed onto a printed substrate or the like, supply of a brazing material and a lead forming processing such as a tie-bar cut or the like can be dispensed with.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプリント基板等へ取付ける加工に有効な半導体
装置の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a semiconductor device that is effective for processing to be attached to a printed circuit board or the like.

〔発明の概要〕[Summary of the invention]

本願において開示される発明の詳細な説明すれば次の通
りである。すなわち、表面を半導体素子が電気的に接続
されるように配線し、外部リード端がスルーホールを介
して裏面ランド部に及ぶ印刷配線板を構成し、メブキ処
理を施した後半導体素子を接着、ボンディング、樹脂モ
ールドと行ないパッケージを形成する。その後ろう材被
着の処理を行なうが、代表的なものに次の二点がある。
A detailed explanation of the invention disclosed in this application is as follows. In other words, a printed wiring board is constructed in which the front surface is wired so that the semiconductor elements are electrically connected, and the external lead ends extend to the rear surface lands via through holes. The package is formed by bonding and resin molding. After that, the brazing metal is deposited, and the following two are typical.

−魚目は溶融はんだ槽等のはんだ処理装置においてスル
ーホールを含むランド部に球面状のろう材突起を形成し
たものである。二魚目はフラックスを含むろう材をスル
ーホール部に打込たんだものである。
- Fish eyes are formed by forming spherical brazing material protrusions on land portions including through holes in solder processing equipment such as molten solder baths. The second type is one in which a soldering material containing flux is driven into the through-hole.

〔従来の技術〕[Conventional technology]

半導体装置の取付は加工を行なう場合、はんだ等のろう
材による接合が多用されるが、半導体装置自体に接合に
有効な量のろう材を含むことは無(加工時に供給されて
いる。
When processing semiconductor devices, bonding using a brazing material such as solder is often used, but the semiconductor device itself does not contain an effective amount of brazing material for bonding (it is supplied during processing).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

半導体装置の製造上のコスト及びプリント基板等への取
付は時のコストを低減させる課題について、製造上にお
いては従来のリードフレームを基材とするものとの比較
でリード加工が削除でき、取付は時においては接合材の
供給が不要となる合理化をねらいとする。
Regarding the issue of reducing the manufacturing cost of semiconductor devices and the cost of mounting them on printed circuit boards, etc., lead processing can be eliminated in manufacturing compared to those using conventional lead frames as the base material, and mounting is easier. In some cases, the aim is to streamline the process by eliminating the need to supply bonding materials.

〔実施例〕〔Example〕

以下、本発明を実施例である図面にしたがって特徴を説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, features of the present invention will be explained with reference to drawings which are embodiments.

第1図は半導体装置のほぼ中心を切る面における°断面
図で、印刷配線板が表面中央部にサライ加工を施した絶
縁基板1.外部リード2.スルーホール3及び裏面ラン
ド部4とにより構成され、接着剤5で半導体素子6を固
定し、ボンディングワイヤー7で電気的に接続した後、
樹脂モールド8でパッケージされている。この場合ろう
材の突起は処理条件を一定としたとき、概ねスルーホー
ルの径及びランド面積により変動する。例えばスルーホ
ールの直径がQ、5mm、スルーホールが中央になるラ
ンド直径がl mvsの場合最大厚み部がQ 、 3 
mm程度となる突起を得る事ができる。スルーホール部
及び裏面ランド部には溶融はんだ槽等のはんだ処理装置
において形成した球面状のろう材突起9が被着されてい
る。このろう材をプリント基板等へ取付は加工するとき
の接合材として利用する。
FIG. 1 is a cross-sectional view taken approximately at the center of a semiconductor device, and shows an insulating substrate 1.A printed wiring board has a roughening process applied to the center of the surface. External lead 2. It is composed of a through hole 3 and a back land portion 4, and after fixing a semiconductor element 6 with an adhesive 5 and electrically connecting it with a bonding wire 7,
It is packaged in a resin mold 8. In this case, the protrusions of the brazing material generally vary depending on the diameter of the through hole and the land area when the processing conditions are constant. For example, if the diameter of the through hole is Q, 5 mm, and the land diameter where the through hole is in the center is l mvs, the maximum thickness part is Q, 3
It is possible to obtain protrusions of about mm. Spherical brazing material protrusions 9 formed in a solder processing apparatus such as a molten solder bath are attached to the through-hole portions and the rear surface land portions. This brazing filler metal is used as a bonding material when attaching to a printed circuit board or the like.

第2図は基本構成が前第1図と同様であるが、フラフク
スを含むろう材10をスルーホール部に打ち込んだ状態
で被着されている。
The basic configuration in FIG. 2 is the same as that in the previous FIG. 1, but a brazing filler metal 10 containing fluff is driven into the through-hole portion and then adhered thereto.

第3図はパッケージ後の印刷配線板が連なる状態を示す
平面図である。予めインデックスマーク11によりメツ
キリ−目2に配線を施すことにより多数個取りを可能と
して、ろう打破着後切断部13を切り離すことにより独
立した半導体装置となる。
FIG. 3 is a plan view showing a state in which printed wiring boards are connected after packaging. It is possible to manufacture a large number of semiconductor devices by providing wiring in advance at the mesh holes 2 using index marks 11, and by separating the cut portions 13 after soldering and bonding, an independent semiconductor device can be obtained.

第4図は一本のリード端子に複数のスルーホールを設け
ろう材の容量を増したリード間隔を狭くする工夫を施し
たもので、第4図fa)はその平面部分図、第4図(b
)は第1図で説明した処理を施しろう材突起14が被着
されている。第4図(C1は第2図で説明した処理が施
したろう材15が複数個被着されている。
Figure 4 shows a device in which multiple through holes are provided in one lead terminal to increase the capacity of the brazing material and to narrow the lead spacing. b
) has been subjected to the treatment described in FIG. 1 and has a brazing material protrusion 14 attached thereto. FIG. 4 (C1 shows a plurality of brazing materials 15 that have been subjected to the treatment described in FIG. 2).

〔発明の効果〕〔Effect of the invention〕

(11プリンl−M板等への取付時に、ろう材供給が不
要である。
(There is no need to supply a brazing material when attaching to a 11 Pudding l-M board etc.

(2)リードフレームを基材とする半導体装置との比較
においてタイバーカット等リード成形加工が不要で製造
の優位性がある。
(2) Compared to semiconductor devices that use lead frames as a base material, there is no need for lead forming processes such as tie bar cutting, and there is a manufacturing advantage.

(3)リードフレームを基材とする半導体装置との比較
において製造工程途中における連続状態での電気的特性
検査が可能である。
(3) In comparison with a semiconductor device using a lead frame as a base material, it is possible to inspect electrical characteristics in a continuous state during the manufacturing process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の断面図、第2図は本発明の他
の実施例の断面図、第3図は本発明の連続状態での平面
図、第4図(a)は本発明の他の実施例の部分平面図、
第4図1b)は他の実施例の部分断面図、第4図(C1
は他の実施例の部分断面図である。 1・・・絶縁基板 2・・・外部リード 3・・・スルーホール 4・・・裏面ランド 5・・・接着剤 6・・・半導体素子 7・・・ボンディングワイヤー 8・・・樹脂モールド 9・・・ろう材 10・・・棒状ろう材 11・・・インデックスマーク 12・・・メッキリード 13・・・切離部 以上 出願人 セイコー京葉工業株式会社 本発明の*紀Vi’lf)断面図 第1図 社の実掩庁jD面面図 第2図 第3図
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of another embodiment of the present invention, FIG. 3 is a plan view of the present invention in a continuous state, and FIG. 4(a) is a sectional view of the present invention. A partial plan view of another embodiment of the invention;
Figure 4 1b) is a partial sectional view of another embodiment, Figure 4 (C1
is a partial cross-sectional view of another embodiment. 1... Insulating substrate 2... External lead 3... Through hole 4... Back surface land 5... Adhesive 6... Semiconductor element 7... Bonding wire 8... Resin mold 9... ... Brazing filler metal 10... Bar-shaped brazing filler metal 11... Index mark 12... Plated lead 13... Separation part and above Applicant: Seiko Keiyo Kogyo Co., Ltd. Cross-sectional view of the present invention No. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims]  スルーホールを有した印刷配線板を基材とし半導体素
子を装着している半導体パッケージにおいて、前記該ス
ルーホール及び該スルーホール周辺部にろう材を被着し
たことを特徴とする半導体装置。
1. A semiconductor device in which a printed wiring board having a through hole is used as a base material and a semiconductor element is mounted thereon, the semiconductor package having a soldering material applied to the through hole and the area around the through hole.
JP62118261A 1987-05-15 1987-05-15 Semiconductor device Pending JPS63283147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62118261A JPS63283147A (en) 1987-05-15 1987-05-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62118261A JPS63283147A (en) 1987-05-15 1987-05-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63283147A true JPS63283147A (en) 1988-11-21

Family

ID=14732248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62118261A Pending JPS63283147A (en) 1987-05-15 1987-05-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63283147A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241133A (en) * 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
JPH0982873A (en) * 1995-09-18 1997-03-28 Nec Corp Semiconductor device and manufacturing method thereof
KR100238197B1 (en) * 1992-12-15 2000-01-15 윤종용 Semiconductor device
KR20020096640A (en) * 2001-06-21 2002-12-31 앰코 테크놀로지 코리아 주식회사 Semiconductor Package & Mounting method to Motherboard the same
US6642624B2 (en) 1999-05-31 2003-11-04 Nec Corporation Ball grid array type semiconductor device
US9530707B2 (en) 2013-10-03 2016-12-27 Fuji Electric Co., Ltd. Semiconductor module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128553A (en) * 1985-11-29 1987-06-10 Kyocera Corp Manufacture of semiconductor package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128553A (en) * 1985-11-29 1987-06-10 Kyocera Corp Manufacture of semiconductor package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241133A (en) * 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
KR100238197B1 (en) * 1992-12-15 2000-01-15 윤종용 Semiconductor device
JPH0982873A (en) * 1995-09-18 1997-03-28 Nec Corp Semiconductor device and manufacturing method thereof
US6642624B2 (en) 1999-05-31 2003-11-04 Nec Corporation Ball grid array type semiconductor device
KR20020096640A (en) * 2001-06-21 2002-12-31 앰코 테크놀로지 코리아 주식회사 Semiconductor Package & Mounting method to Motherboard the same
US9530707B2 (en) 2013-10-03 2016-12-27 Fuji Electric Co., Ltd. Semiconductor module

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