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JPS63282261A - Sputtering device - Google Patents

Sputtering device

Info

Publication number
JPS63282261A
JPS63282261A JP11846287A JP11846287A JPS63282261A JP S63282261 A JPS63282261 A JP S63282261A JP 11846287 A JP11846287 A JP 11846287A JP 11846287 A JP11846287 A JP 11846287A JP S63282261 A JPS63282261 A JP S63282261A
Authority
JP
Japan
Prior art keywords
target
semiconductor wafer
space
wafer
sputtering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11846287A
Other languages
Japanese (ja)
Inventor
Toru Takane
高根 亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11846287A priority Critical patent/JPS63282261A/en
Publication of JPS63282261A publication Critical patent/JPS63282261A/en
Pending legal-status Critical Current

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  • Physical Vapour Deposition (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To prevent the generation of dust and to improve the operation rate of the title device by providing a shielding plate on the whole side of a space between the target and semiconductor wafer in a sputtering chamber. CONSTITUTION:A target 2 held on a support 3 and used for sputtering a metal atom and a wafer stage 4 held on a support 5 and used for holding a semiconductor wafer 10 are arranged in the sputtering chamber 1. The metal atom from the target 2 is deposition on the semiconductor wafer 10 to form a thin metal film. In such a sputtering device, the cylindrical shielding plate 6 is provided to cover the periphery of the support 3, the periphery of the target 2, the whole side of the space between the target 2 and the semiconductor wafer 10, and the whole periphery of the wafer stage 4 with a gap of about 1-2mm in between. By this method, the splashing of the metal atom to the outside of the space between the target 2 and the semiconductor wafer 10 can be controlled to a minimum.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はスパッタ装置に関し、特にターゲットから金属
原子を飛散させ半導体ウェーハ上に金属薄膜を形成させ
る薄膜形成装置の中のスパッタ装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sputtering apparatus, and particularly to a sputtering apparatus in a thin film forming apparatus that scatters metal atoms from a target to form a metal thin film on a semiconductor wafer.

〔従来の技術〕[Conventional technology]

従来、この種のスパッタ装置は、第3図に示すように、
所定の真空度を保つスパッタチャンバー1と、このスパ
ッタチャンバー1内に設けられターゲット支柱3に保持
されて金属原子を飛散させる為のターゲット2と、この
ターゲット2の金属原子の飛散面を除く周囲を覆う為の
ターゲットシールド板8と、半導体ウェーハ10を保持
しこの半導体ウェーハ10上に金属薄膜を形成させる為
のウェーハステージ4と、金属原子が半導体ウェーハ1
0の外側周辺への飛散するのを防ぐ為のつ工−ハシール
ド板9と、ウェーハステージ4を支える為のステージ支
柱5とを有する構成となっていた。
Conventionally, this type of sputtering apparatus, as shown in FIG.
A sputtering chamber 1 that maintains a predetermined degree of vacuum, a target 2 provided in this sputtering chamber 1 and held by a target support 3 to scatter metal atoms, and a surrounding area of this target 2 excluding the surface on which metal atoms are scattered. a target shield plate 8 for covering the semiconductor wafer 10; a wafer stage 4 for holding the semiconductor wafer 10 and forming a metal thin film on the semiconductor wafer 10;
The structure includes a wafer shield plate 9 for preventing the wafer from scattering to the outer periphery of the wafer, and a stage support 5 for supporting the wafer stage 4.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のスパッタ装置は、ターゲット2の周囲と
半導体ウェーハ10のみがそれぞれシールド板で覆われ
ていてこれらの間の空間は開放された構造となっている
ので、ターゲット2から飛散した金属原子がスパッタチ
ャンバー1内の側壁等に付着しごみの発生の原因になっ
たり、スバ・ンタ装置の点検や清掃が困難になり稼働率
が低下するという問題点がある。
In the conventional sputtering apparatus described above, only the periphery of the target 2 and the semiconductor wafer 10 are covered with shield plates, and the space between them is open, so that the metal atoms scattered from the target 2 are There are problems in that it adheres to the side walls of the sputtering chamber 1 and causes dust, and that it becomes difficult to inspect and clean the sputtering apparatus, reducing the operating rate.

本発明の目的は、ターゲットからの金属原子がターゲッ
トと半導体ウェハとの間の空間の外側に飛散するのを最
小限に抑え、ごみの発生を防止し点検や清掃が容易にな
り、稼働率を向上させることができるスパッタ装置を提
供することにある。
The purpose of the present invention is to minimize the scattering of metal atoms from the target to the outside of the space between the target and the semiconductor wafer, prevent the generation of dust, facilitate inspection and cleaning, and improve the operating rate. The object of the present invention is to provide a sputtering apparatus that can be improved.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のスパッタ装置は、スパッタチャンバー内に設け
られた、金属原子を飛散させるためのターゲットと、半
導体ウェーハを保持しこの半導体ウェーハ上に前記ター
ゲットからの金属原子を堆積させ金属薄膜を形成される
ウェーハステージと、前記ターゲットからの金属原子が
周囲に飛散しないように少なくともこのターゲットと前
記半導体ウェーハとの間の空間の側面全面に設けられた
シールド板とを有している。
The sputtering apparatus of the present invention includes a target provided in a sputtering chamber for scattering metal atoms, and a semiconductor wafer that is held, and metal atoms from the target are deposited on the semiconductor wafer to form a metal thin film. The device includes a wafer stage and a shield plate provided on the entire side surface of at least the space between the target and the semiconductor wafer so that metal atoms from the target are not scattered around.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例を示す一部断面側面図で
ある。
FIG. 1 is a partially sectional side view showing a first embodiment of the present invention.

この実施例は、所定の真空度を保つスバ・7タチヤンパ
ー1内に設けられターゲット支柱3に保持されて金属原
子を飛散させるターゲット2と、半導体ウェーハ10を
保持しこの半導体ウエーノ110上に金属原子を堆積さ
せて金属薄膜を形成させるウェーハステージ4と、この
ウェーハステージ4を支えるステージ支柱5と、ターゲ
ット2からの金属原子が周囲に飛散しないように、ター
ゲット2と半導体ウェーハ10との間の空間の側面全面
、及びターゲット支柱3.ターゲット2及びウェーハス
テージの周囲に設けられたシールド板6と、このシール
ド板6を支えるシールド板支柱7とを有する構成となっ
ている。
This embodiment includes a target 2 which is provided in a vacuum cleaner 1 that maintains a predetermined degree of vacuum, is held by a target support 3, and scatters metal atoms, and a semiconductor wafer 10 is held and metal atoms are deposited on the semiconductor wafer 110. A wafer stage 4 on which a thin metal film is deposited, a stage support 5 that supports this wafer stage 4, and a space between the target 2 and the semiconductor wafer 10 to prevent metal atoms from the target 2 from scattering to the surroundings. The entire side surface of and the target support 3. The structure includes a shield plate 6 provided around the target 2 and the wafer stage, and a shield plate support 7 that supports the shield plate 6.

第1図において、ターゲット支柱3の周囲、ターゲット
2の周囲、ターゲット2と半導体ウェーハ10との間の
距離7〜8CIIlの空間の側全面及びウェーハステー
ジ4の周囲のすべてを隙間1〜21m程度で覆うような
厚さ5〜10+a+aの円筒状のシールド板6を設ける
ことにより、ターゲット2と半導体ウェーハ10との間
の空間の外側への金属原子の飛散を最小限に抑えること
ができる。これにより、スパッタチャンバー1内の清掃
が容易になり労力を大幅に低減することができる。
In FIG. 1, the area around the target support 3, the area around the target 2, the entire side of the space between the target 2 and the semiconductor wafer 10 at a distance of 7 to 8 CIIl, and the area around the wafer stage 4 are all covered with a gap of about 1 to 21 m. By providing a covering cylindrical shield plate 6 with a thickness of 5 to 10+a+a, scattering of metal atoms to the outside of the space between the target 2 and the semiconductor wafer 10 can be minimized. This makes it easy to clean the interior of the sputtering chamber 1, and the labor required can be significantly reduced.

また、シールド板6を着脱可能とすることにより、スパ
ッタチャンバー1内の点検が容易になるとともにスパッ
タチャンバー1内の清掃の大半がシールド板6を交換す
るのみで終了する為、スパッタ装置の稼働率が大幅に向
上する。
In addition, by making the shield plate 6 removable, inspection inside the sputter chamber 1 becomes easier, and most of the cleaning inside the sputter chamber 1 can be completed by simply replacing the shield plate 6, which increases the operating efficiency of the sputtering equipment. will be significantly improved.

第2図は本発明の第2の実施例を示す一部断面側面図で
ある。
FIG. 2 is a partially sectional side view showing a second embodiment of the invention.

この実施例が第1の実施例と相違する点は、シールド板
をターゲット2及びターゲット支柱3の周囲を覆うター
ゲットシールド板8とターゲット2と半導体ウェー/>
 l Qとの間の空間側面全面を覆うシールド板6aと
に分離した点にあり、スパッタチャンバー1内の点検、
清掃が更に容易になるとともにシールド板6aの着脱も
更に容易になるという利点がある。
This embodiment differs from the first embodiment in that a target shield plate 8 covers the target 2 and the target support 3, and a target 2 and semiconductor wafer.
It is located at a point separated from the shield plate 6a that covers the entire side surface of the space between the sputtering chamber 1 and the sputter chamber 1.
This has the advantage that cleaning becomes easier and attachment and detachment of the shield plate 6a becomes easier.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、少なくともターゲットと
半導体ウェーハとの間の空間側面全面をシールド板で覆
う構成とすることにより、ターゲットからの金属原子が
ターゲットと半導体ウェーハとの間の空間の外側に飛散
するのを最小限に抑えることができ、スパッタチャンバ
ー内のごみの発生を防止し点検、清掃を容易にし、スパ
ッタ装置の稼働率を向上させることができる効果がある
As explained above, the present invention has a structure in which at least the entire side surface of the space between the target and the semiconductor wafer is covered with a shield plate, so that metal atoms from the target are directed to the outside of the space between the target and the semiconductor wafer. This has the effect of minimizing scattering, preventing the generation of dust in the sputtering chamber, facilitating inspection and cleaning, and improving the operating rate of the sputtering apparatus.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示す一部断面側面図、
第2図は本発明の第2の実施例を示す一部断面側面図、
第3図は従来のスパッタ装置の一例を示す一部断面側面
図である。 1・・・スパッタチャンバー、2・・・ターゲット、3
・・・ターゲット支柱、4・・・ウェーハステージ、5
・・・ステージ支柱、6,6a・・・シールド板、7・
・・シールド板支柱、8・・・ターゲットシールド板、
9・・・ウェーハシールド板、10・・・半導体ウェー
ハ。 代理人 弁理士 内 原  晋ρ 7スIv・・l夕+ヤワノマー 第1図 第21¥ll
FIG. 1 is a partially sectional side view showing a first embodiment of the present invention;
FIG. 2 is a partially sectional side view showing a second embodiment of the present invention;
FIG. 3 is a partially sectional side view showing an example of a conventional sputtering apparatus. 1... Sputter chamber, 2... Target, 3
...Target support, 4...Wafer stage, 5
...Stage support, 6, 6a...Shield plate, 7.
...Shield plate support, 8...Target shield plate,
9... Wafer shield plate, 10... Semiconductor wafer. Agent Patent Attorney Susumu Uchihara 7th Iv...l Yu+Yawanomer Figure 1 21 ¥ll

Claims (1)

【特許請求の範囲】[Claims]  スパッタチャンバー内に設けられた、金属原子を飛散
させるためのターゲットと、半導体ウェーハを保持しこ
の半導体ウェーハ上に前記ターゲットからの金属原子を
堆積させ金属薄膜を形成されるウェーハステージと、前
記ターゲットからの金属原子が周囲に飛散しないように
少なくともこのターゲットと前記半導体ウェーハとの間
の空間の側面全面に設けられたシールド板とを有するこ
とを特徴とするスパッタ装置。
A target provided in a sputtering chamber for scattering metal atoms; a wafer stage that holds a semiconductor wafer and deposits metal atoms from the target onto the semiconductor wafer to form a metal thin film; 1. A sputtering apparatus comprising a shield plate provided at least on the entire side surface of a space between the target and the semiconductor wafer to prevent metal atoms from scattering to the surrounding area.
JP11846287A 1987-05-14 1987-05-14 Sputtering device Pending JPS63282261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11846287A JPS63282261A (en) 1987-05-14 1987-05-14 Sputtering device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11846287A JPS63282261A (en) 1987-05-14 1987-05-14 Sputtering device

Publications (1)

Publication Number Publication Date
JPS63282261A true JPS63282261A (en) 1988-11-18

Family

ID=14737255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11846287A Pending JPS63282261A (en) 1987-05-14 1987-05-14 Sputtering device

Country Status (1)

Country Link
JP (1) JPS63282261A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0676793A2 (en) * 1994-04-06 1995-10-11 Canon Sales Co., Inc. Substrate holder and reaction apparatus
US5460708A (en) * 1990-11-30 1995-10-24 Texas Instruments Incorporated Semiconductor processing system
CN115286257A (en) * 2022-08-03 2022-11-04 王凯泽 ITO glass coating system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5460708A (en) * 1990-11-30 1995-10-24 Texas Instruments Incorporated Semiconductor processing system
EP0676793A2 (en) * 1994-04-06 1995-10-11 Canon Sales Co., Inc. Substrate holder and reaction apparatus
EP0676793A3 (en) * 1994-04-06 1998-01-21 Canon Sales Co., Inc. Substrate holder and reaction apparatus
CN115286257A (en) * 2022-08-03 2022-11-04 王凯泽 ITO glass coating system

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