JPS63280458A - Manufacturing method of vertical MOS semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the increase in chip area by a method wherein the ion- implantation process is applied for the purpose of forming an N<+> layer and a P<+> layer using the polysilicon pattern which is formed simultaneously with a polysilicon gate. CONSTITUTION:Boron, which is used as acceptor impurities, is implanted into an N<-> epitaxial layer 32 by conducting an ion implanting method using a polysilicon gate 38 and a polysilicon pattern 39 as a mask, and P<-> layers 40, which become a second conductivity layer having the desired depth, is formed by conducting a heat treatment. At this time, a polysilicon pattern 39 is formed in such a manner that the two P<-> layers 40 will be superposed on the part located directly under the polysilicon pattern 39. Then the same masks, namely, the polysilicon gate 30 and the polysilicon pattern 39 are used as masks, the donor impurities such as arsenic or phosphorus are implanted into the P layer 40 using an ion implantation method. After an N<+> layer 41, which becomes a third conductivity layer, has been formed in the P<-> layer 40 by conducting a heat treatment, an oxide film 42 is formed by performing a thermal oxidization method.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a double-diffused vertical MO8 semiconductor element used in a power MO8 transistor.

(Prior Art) Conventionally, regarding the manufacturing method of a vertical MO8 semiconductor element, for example, in 1985, IEEE IEDM TECHNI
CAL DIGEST (IEEI IEDM Technical Digest) 146-1
Page 48: A report titled ``Method for manufacturing an absolute R gate in a transistor,'' and ``Japanese Patent Application Laid-Open No. 5'7-88772.
It is known from "No. Publication".

FIGS. 2(&) to 2(f) are diagrams showing the steps of a conventional method for manufacturing a vertical MO8 semiconductor device. first.

As shown in FIG. 2(a), after forming an N″″″ epitaxial layer 2 on a N medium substrate 1, an sr-) oxide film 3, a polysilicon film 4 are sequentially formed, and phosphorus is diffused over the entire surface. to provide conductivity.

Next, as shown in FIG. 2(b), the polysilicon film 4 is etched by normal photoetching to form an opening 5 and a polysilicon f-hole.

Next, as shown in FIG. 2(c), using the polysilicon gate 6 as a mask, ions are implanted into the N-epitaxial layer 2 by ion implantation, and a P layer 7 of a desired depth is formed by heat treatment. do.

Next, as shown in FIG. 2(d), a resist 8 is formed by ordinary photolithography to cover the central part of the P layer 7, and then the resist 8 and polysilicon r-) 6 are used as a mask. , arsenic or phosphorus 1kp by ion implantation method
One layer 7 is implanted, and a ten-N layer 9 is formed by heat treatment.

Next, as shown in FIG. 2 (<6), after removing the renost 8, a resist 10 is formed by normal photolithography so that the portion covered with the resist 8 as shown in FIG. 2 (d) is opened. Then, using this resist lO as a mask, a P'''' layer 7 of poron is implanted by ion implantation, and a P+ layer 1 for forming contact with metal is formed by heat treatment.

Next, as shown in FIG. 2(f), a PSG film 12 is formed, and the PSG film 12 is etched by normal photoetching.
After etching the chemical film 3 to form a contact opening 13, an electrode 14 which will become a contact hole is formed.

Further, an electrode 18 serving as a drain is also formed on the N+ substrate l side. In this way, a double-diffused vertical MO8 semiconductor device with a polysilicon gate is formed.

(Problems to be Solved by the Invention) However, in such a conventional manufacturing method, the photolithography of the V cyst 8t, which serves as a mask for forming the N0 layer 9, and the right-handed photolithography for forming the P0 layer 11 ．． A ninth photolithography process is required to form a resist lO that serves as a mask for the formation of .

For this reason, there is no need for extra dimension for alignment during photolithography, and as a result, the contact opening 13 shown in FIG.
The contact diameter increases by the above-mentioned alignment margin.

For products such as the NORMAL MO8 that use the shape shown in Figure 2 as the minimum unit structure (cell) of tens of thousands to 100,000 cells, an increase in the contact diameter due to the alignment margin will greatly increase the chip area. be.

The present invention provides a method for manufacturing a mounting MO8 semiconductor device that solves the problem of the contact diameter increasing due to the alignment margin, among the problems of the prior art.

(Means for solving the problem) This invention is vertical! In a method for manufacturing an MO8 semiconductor device,
A process is introduced in which ions are implanted to form an N middle layer and a p+ layer using a polysilicon gate formed at the same time as the polysilicon gate.

(Function) According to the present invention, since the above steps are introduced into the method for manufacturing a vertical fiMO8 semiconductor device, the N middle layer and the 21
A layer can be formed on the polysilicon gate and self-line,
It acts to eliminate the alignment margin.

Therefore, the above-mentioned problem can be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a vertical MO8 semiconductor device of the present invention will be described based on the drawings.

First, as shown in FIG. 1(a), an N-epitaxial layer 32t, which becomes a first conductivity type layer, is formed on an N-substrate 31. Next, on the KN-epitaxial layer 32, an R-type trench film 33 and a conductive polysilicon film 34 are sequentially formed, and after diffusing phosphorus over the entire surface to make it conductive, oxidation [ 35 is formed on the polysilicon gate, and then a nitride film 36t- is formed.

Next, as shown in FIG. 1(b), the nitride film 36 and oxide film 35 other than the r-type oxide film 33 are etched by normal photoetching.
, the polysilicon R34 is etched to form an opening 37, and a polysilicon pattern 39 is formed at the center of the polysilicon gate 38 and the ends of the two polysilicon gates.

Next, as shown in FIG. 1(e), an N-epitaxial layer 32 is formed by ion implantation using a polysilicon r-t3B, If IJ silicon/9-turn 39t-mask.
No. 2, which is an accessor impurity, is implanted into the substrate, and heat treatment is performed to form a P layer 40 having a desired depth and serving as a second conductivity type layer. At this time, a polysilicon film turf 39 is formed so that the two P layers 40 overlap directly under the polysilicon pattern 39.

Next, use the same mask, i.e. polysilicon gate 38.
Then, using the silicon pattern 39 as a mask IC, ion implantation is used to implant arsenic or phosphorus as a donor impurity into the P layer 40, and heat treatment is performed to form the N+ layer 41, which will become the third conductive layer, into the P layer 40. After forming the oxide film 42t-
Form.

Next, as shown in FIG. 1(d), after removing the nitride film 36 with hot phosphoric acid, the opening 37 is removed by ordinary photolithography.
A resist 43 is formed to cover the polysilicon film turns 39. At this time, the polysilicon nine-turn turn 39 and the resist 43 may be aligned to such an extent that the opening of the resist 43 does not cover the polysilicon gate 38.

Next, as shown in FIG. 1(6), using the resist 43 as a mask, the oxide film 35 on the polysilicon turns 39 is removed by normal etching, and then the polysilicon pattern 39 is removed by dry etching. Remove by etching.

After this, when the resist 43 is removed, an oxide film pattern consisting of a concave oxide film 42 with depressions formed where the polysilicon nine turns 39 were formed is completed.

Using this oxide film/lean as a mask, a layer of P4 is added using the ion implantation method.
When boron, which is an accessor impurity, is implanted into 0, boron is implanted only into the concave portions, and a P+ layer 44 is formed as a fourth conductivity type layer by heat treatment.

Next, as shown in FIG. 1(f), after forming the PSG 45t, this P4O10 and oxide film 42. The r-to oxide film 33 is etched to expose the %N layer 1 and the P+ layer 44, and a contact opening 46 having a diameter of a hole is formed.

Thereafter, an electrode 47 that will serve as a source is formed, and an electrode 48 that will serve as a drain is also formed on the N-substrate 31 side, thus forming an N-channel double-diffusion type MO8 semiconductor device.

Note that the above embodiment has a structure using a lower drain electrode, but if the drain electrode is formed from the upper part, PN separation and
It can also be applied to vertical MO8 semiconductors with DI separation.

(9) In the above embodiment, an N-channel MO84C is shown, but it goes without saying that it can be easily applied to a P-channel MO8 by changing the valley conductivity type.

(Effects of the Invention) As described above in detail, according to the present invention, masks for ion implantation of the N+ layer and P+ layer within the P layer are formed simultaneously with the formation of the polysilicon gate, and 7. Since the TT polysilicon pattern is used, there is no need for a margin for alignment with the polysilicon gate.

Along with this, it is possible to reduce the contact diameter by the size of the alignment margin for the two photolithography steps that were conventionally performed. Therefore, power transistors that use tens of thousands to one million minimum unit structures (cells) This has the effect of reducing the chip area.

[Brief explanation of the drawing]

FIG. 1(a) to FIG. 1(f) are vertical MOs of the present invention.
8. Process explanatory diagram of one embodiment of the method for manufacturing semiconductor devices, 2nd
Figures (a) to 2(f) are process explanatory diagrams of a conventional method for manufacturing a vertical MO8 semiconductor element. 31... N-child substrate, 32... N- epitaxial layer, 33... r-) oxide film, 34... polysilicon film, 35.42... oxide film, 36... nitride film , 37・
・・Opening part, 38...-Resilicon r-1, 39...
・Polysilicon pattern, 40...P″″ layer, 41・
...N+ layer% 43...Renost, 44...P" layer, 45...PSG, 46...Contact opening, 4
7.48...electrode. Non-standard size grass type NOδ 〒Den I Honki Shihe made incorrectly revised Taisho tヱPrison Figure 1 Conventional wood grass type MOδ↑ Monument Banmineshi No. 2L ・Nashi'M direction Engineering fヱconcave

Claims (1)

[Claims] (a) A gate oxide film is formed on a first conductivity type layer forming a semiconductor element, a conductive polysilicon film is formed on the gate oxide film, and then an oxide film is formed on the gate oxide film. (b) forming a hole with the gate oxide film remaining;
simultaneously forming a pair of polysilicon gates and forming a polysilicon pattern in an intermediate portion of the pair of polysilicon gates; (c) using the pair of polysilicon gates and the polysilicon pattern as a mask; In the first conductivity type layer,
A pair of second conductivity type layers that are of a different conductivity type from the first conductivity type layer and overlap directly below the polysilicon pattern; 1
forming a third conductivity type layer of the same conductivity type as the conductivity type layer by implanting impurity ions, and then forming an oxide film on the third conductivity type layer by heat treatment; (d) nitriding the entire surface; After removing the film and removing the oxide film on the polysilicon pattern, the polysilicon pattern is removed and a fourth conductivity type layer having the same conductivity type as the second conductivity type layer is formed in the removed portion. (e) After forming an intermediate insulating film, openings are formed so as to span the third and fourth conductivity type layers, and then electrodes are formed. A method for manufacturing a vertical MOS semiconductor device, comprising the steps of: