JPS63276790A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To obtain a one-TR/one-cell memory with one layer of Al wiring forming a memory cell by connecting an enhancement type MOS transistors (TR) whose source or drain is shortcircuited to one substrate and the remain is not shortcircuited, in series. CONSTITUTION:A memory cell is formed with the n-type enhancement MOSTR 131 whose drain is shortcircuited to a p-type substrate, etc. and the that TR 133 whose source and the drain of are connected in series and whose source is connected with a signal line 102. When the drain of the TR 131 is operated as a drain through the signal line 101 connected to the said drain, the TR 131 is turned on at all time irrespective of its gate potential, while if its drain is operated as a source, the TR 131 operates as an ordinary enhancement TR and goes to normally off state. Such a storaging state is read out by turning on the TR 133 through a signal line 112. In such constitution, a need for crossing the signal line connected to a drain and that connected to a source in wiring can be eliminated, hence a nonvolatile memory of one-TR/one cell can be obtained with use of one layer of Al wiring.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention puts an enhanced MOS transistor whose source or drain is electrically shorted to the substrate into a writing state, and puts the enhanced MOS transistor into a non-writing state. The present invention relates to a semiconductor nonvolatile memory in which a plurality of memory elements to be used as states are arranged in a matrix, and in particular to high integration by eliminating switching elements called address transistors from the matrix.

[Conventional technology]

The type with the highest degree of integration among semiconductor nonvolatile memories is called the ITr/1 cell type.
One bit consists of only one memory element. In the case of a read-only memory or a read-only memory that can be written only once, memory elements whose drain electrodes are connected to the same signal line can be arranged so that their source and gate electrodes are connected to different signal lines. It is well known that the ITr/1 cell system is possible because addressing is possible whether the memory element is normally on or normally off. Such an example is shown in FIG.

The memory matrix in FIG. 3 includes memory elements 331
．． 362.666.634, and different signal lines 301 connected to the drain electrodes.
．． 302, different signal lines 311, 612 connected to the gate electrode, and different signal lines 321, 622 connected to the source electrode.

For example, when reading data from the memory element 631, the signal line 3 connected to the drain electrode of the memory element 631
01 and the signal line 611 connected to the gate electrode of this memory element 361 or the signal line 321 connected to the source electrode of this memory element 661, address transistors are not required.

[Problem that the invention seeks to solve]

However, the fact that the signal line connected to the drain and the signal line connected to the source must be wired so that they intersect means that it is not possible to wire both with a single layer of aluminum; It was necessary to devise measures such as forming a layer or forming one of the wirings with a diffusion layer.

Double-layer aluminum wiring increases manufacturing costs, so normally diffusion layer wiring is used, but since the resistance of the diffusion layer is orders of magnitude higher than that of aluminum, the time constant of the wiring is extremely large. , there was a problem that it hindered high-speed operation.

It is well known that the so-called 2Tr/1 cell system, in which an address transistor is added to each memory element, does not require diffusion layer wiring, but it is clear that it is disadvantageous in terms of integration. It is.

Therefore, an object of the present invention is to
This provides a means to enable the T r /1 cell system.

[Means for solving problems]

A feature of the present invention is that a plurality of enhanced type M
OS transistors and source motoranes also use a combination of any two of the multiple enhanced MO3) transistors that are not electrically shorted to the board, and the terminals that are not electrically shorted to the board are contacts. The two transistors are connected in series so that the gate electrodes of the two transistors are connected to different signal lines, and are arranged in a matrix as one unit.

[Effect]

The reason why the configuration of the present invention enables the I T r /1 cell system is that each memory element functions as an address transistor for an adjacent memory element connected in series.

〔Example〕

The following description based on examples will make it clear how the features of the invention solve the problems.

FIG. 2 shows an embodiment of an enhanced type MOS transistor used as a memory element in the present invention, and shows a cross section of the basic part.

The Enno-nce type MOS transistor in Fig. 2 is n
This is an example of a channel, with a substrate 201 on a p-type substrate 201.
It has a p-type diffusion region 202 to facilitate connection with the tray 7206, an n-type drain 206 and an n-type source 204, and a drain electrode 211 connected to the p-type diffusion region 202 and the tray 7206 at the same time. A source electrode 212 is provided, and a gate electrode 213 is provided on a gate insulating film 221 .

In FIG. 2, if a positive voltage is applied to the drain electrode 211 with respect to the source electrode 212, the p-type substrate 201 and n
Since the p-n junction diode consisting of the shaped source 204 is in the forward direction, the drain electrode 211 and the source electrode 212
becomes conductive regardless of the potential of the gate electrode 216.

On the other hand, the source electrode 2 with respect to the drain electrode 211
When applying a positive voltage to the substrate 20, the n-type diffusion region 204 functions as a drain and the n-type diffusion region 203 functions as a source.
Even if it is short-circuited to 1, it operates as a normal enhanced type MOS transistor.

In other words, the structure shown in Figure 2 depends on whether the side shorted to the substrate is used as a source or a drain.
It can be used either as a normal enhanced MOS transistor or as a normally conductive element. Since a normal enhanced type MOS transistor is normally off, it can be distinguished from a normally conductive state with the shorted side as the drain, and therefore can be used as a memory.

Note that any means may be used to short-circuit with the substrate.

Furthermore, the same effect can be obtained even if a p-channel is used.

FIG. 1 shows an embodiment of a memory matrix according to the present invention. The memory matrix consists of memory elements 131.162.133.134 used in the invention, each having a different signal line 101.102 connected to the source or drain electrode, which may be shorted to the substrate, and the gate Different signal lines 111.11 connected to the electrodes
2.116.114.

The contacts between the memory elements are on the side that is not short-circuited to the substrate, and the side connected to the signal line 101 or 102 may or may not be short-circuited to the substrate depending on the state of writing information.

As is clear from the above explanation of FIG. 2, if the signal line 101 is used as a source, regardless of the writing state of each memory element, the memory elements 131 and 162 connected to the signal line 101 will be By operating as a normal enhancement type MOS transistor and using the signal line 102 as a source, the memory elements 166 and 164 connected to this signal line 102 operate as a normal enhancement type MOS transistor.

Therefore, for example, when reading information from memory element 161, the signal line 101 connected to this memory element 131 is used as the drain, the signal line 102 connected to the memory element 133 connected in series to this memory element 161 is used as the source,
Signal line 1 connected to the gate electrode of this memory element 136
12 to make the memory element 136 conductive, and the signal lines 111, 116, and 114 of the other gates are turned OFF.
Let's make it v. If the memory element 131 from which information is to be read is in a write state, the signal line 101 connected to this memory element 161 is set as a drain, and since this memory element 131 is always in a conductive state, the signal line 101 connected to this memory element 161 is set as a drain. line 101 and signal line 102 as source
During this period, conduction occurs through the memory element 131 and the adjacent memory element 163.

If the memory element 131 from which information is to be read is in a non-writing state, it will be in a non-conducting state unless a voltage is applied to the signal line 111 connected to the gate electrode of the memory element 161. A non-conducting state occurs during the source signal a102. At this time, even if the memory element 162 that shares the signal line 101 used as a drain is in a conductive state, the memory element 134 connected in series to this memory element 132 is in a non-conductive state, so an attempt is made to read information. There is no problem in reading information from the memory element 161. In other words, since the memory element 136 connected in series functions as an address transistor for the memory element 131 from which information is to be read, it is possible to read only the information of the memory element 131 from which information is to be read. It becomes possible.

When reading information from other memory elements, each adjacent memory element is used as an address transistor in the same way, and the fact that one element plays the dual role of a memory element and an address transistor means that IT
This is the reason why r/1 cells are possible.

In FIG. 1, signal line 111. connected to the gate electrode.
112, 113, and 114 are normally made of polycrystalline silicon or the like used for gate electrodes and are used as wiring, so there is no problem in intersecting aluminum wiring.

Since the signal lines 101 and 102 connected to the source or drain electrodes, which may be short-circuited to the substrate, do not intersect, it can be formed with a single layer of aluminum wiring.

Therefore, if a matrix is constructed as shown in FIG. 1, an I T r/l cell system can be achieved with a single layer of aluminum wiring.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the I T r/l cell system is possible with a single layer of aluminum wiring, and its effects are very large. In particular, the effect is even more significant when applied to large-capacity memories, where the area of the memory section greatly affects signal propagation speed and chip size.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a memory matrix in an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an embodiment of an Enno-nce type MOS transistor used as a memory element in the present invention. , FIG. 3 is a circuit diagram showing the configuration of a memory matrix according to the prior art. 101.102.111.112.116.114...
...Signal line, 131.132.136.164...Memory element. First cause 13L132.133.134. Memory base figure 2

Claims (1)

[Claims] An enhanced MOS transistor whose source or drain terminal is electrically short-circuited to the substrate is set to a write state, and the enhanced MOS transistor is set to a non-write state.
An arbitrary combination of two enhanced MOS transistors are connected in series so that the terminals electrically insulated from the substrate are in contact with each other, and the gate electrodes of the two enhanced MOS transistors are connected to different signal lines. A semiconductor non-volatile memory characterized by arranging things in a matrix as a unit.