JPS63273135A - central processing unit - Google Patents

Abstract

PURPOSE:To attain high speed operation by providing a 2nd program counter and an instruction decoder at least for the entire machine language instruction switch-to-macro instruction and next instruction to define and execute a macro instruction. CONSTITUTION:When a switch-to-macro instruction is decoded by an instruction decoder 18, a central processing unit (CPU) jumps to am start address of a macro instruction commanded by the 2nd program counter an executes sequentially plural machine language instructions constituting the macro instruction. When a next instruction is decoded by the instruction decoder 18, the processing of the CPU jumps to the content of the address commanded by the 2nd program counter 16 to execute the macro instruction, and sets the start address of the macro instruction to be executed next in the 2nd program counter 16. Thus, the definition and execution of the macro instruction are made possible and it is not required to jump to the routine at each execution of each macro instruction, and high speed operation is attained.

Description

Detailed Description of the Invention [Summary] The present invention is a central processing unit that has a second program counter and an instruction decoder for all machine language instructions including at least switch-to-macro instructions and next instructions. can be defined and executed, enabling high-speed operation and reducing the number of program bytes.

(Field of Industrial Application) The present invention relates to a central processing unit, and more particularly, to a central processing unit that sequentially executes each machine language instruction of an object program.

Central processing unit! (CPU) transfers data between registers,
Processing is executed by a combination of basic operations such as memory access, digit shifting, and shifting.

Generally, a CPU can only decode machine language instructions, and the object program executed by the CPU is composed of machine language instructions that instruct each of the above-mentioned basic operations.

[Conventional technology]

Generally, when a CPU wants to repeatedly execute a set of procedures, the set of procedures is defined as a subroutine. When a subroutine is called while the CPU is executing a main routine, the CPU jumps to that subroutine, executes the subroutine, returns to the main routine after completion, and executes the main routine.

When different subroutines are executed successively, the object program has a structure as shown in FIG. Fourth
In the figure, the address n of the main routine is 1, for example.
A byte jump subroutine (JSR) instruction is written, and the subroutine start address S of 2 bytes is written at the next address n+1.

When the CPU reads and decodes the JSR instruction, it stacks the address n+3 indicated by the program counter at that time, jumps to address S, and executes the subroutines written in order from address S. A RETURN instruction is assigned at the end of each subroutine, and when CPLJ executes the RE T tJ RN instruction, it returns the address from the stack to the address pointer and returns to address n+a.

[Problem that the invention seeks to solve]

As shown in Figure 4, when different subroutines are executed consecutively, the CPU jumps from the main routine to the subroutine for each subroutine, and then jumps back to the main routine after the subroutine has finished executing, making high-speed operation impossible. 3 with starting address
Since each subroutine is executed using bytes, there is a problem in that the main routine of the object program requires a large number of bytes.

Also, in macro assembly languages such as FORTH,
It is also possible to define a procedure similar to the above subroutine as the macro instruction WARD, but in this case, the CP
There was a problem in that an interpreter had to be provided inside the U, and high-speed operation was not possible.

The present invention has been made in view of the above points, and an object of the present invention is to provide a central processing unit that can define and execute macro instructions, can operate at high speed, and can reduce the number of bytes of an object program. shall be.

[Means for solving problems]

The central processing unit of the present invention includes a second program counter (16) that indicates the address storing the start address of the next macro instruction to be executed in the macro instruction execution mode, and a 210th program counter (16) that indicates the start address of the macro instruction to be executed next in the macro instruction execution mode. Decoding of all machine language instructions including at least a switch-to-macro instruction that instructs to set the address of the second program counter (16) and a next instruction that instructs the execution of the next macro instruction and the resetting of the address of the second program counter (16). and an instruction decoder (18) for executing macro instructions defined by a set of a plurality of machine language instructions.

(Operation) In the present invention, the instruction decoder (18)
When the second macro instruction is decoded, the CPU enters the macro instruction execution mode and decodes the next macro instruction to be executed.
The n start address is stored, and the n address is set in the second program counter (16), and the CPU jumps to the content of the address indicated by the second program counter, that is, the start address of the macro instruction, and executes the multiple instructions constituting the macro instruction. Executes machine language instructions sequentially.

Furthermore, when the next instruction is decoded by the instruction decoder (18), the CPU jumps to the contents of the address indicated by the second program counter (16), executes the macro instruction, and Sets the start address of the macro instruction to be executed next.

This allows the definition and execution of macro instructions.

In addition, since the second program counter (16) indicates the address where the start address of the next macro instruction is stored, there is no need to jump to the main routine each time the macro instructions are executed. High-speed operation is possible.

〔Example〕

FIG. 1 shows a block system diagram of an embodiment of a central processing unit (CPU) of the present invention.

In the figure, 10 is an internal data bus, which is connected to an external data bus via a terminal 11.

The register array 12 is arranged with various registers that store values supplied from the internal data bus 10, and includes a stack pointer 14.
A program counter 15 is provided as well as a second program counter 16. This register
The address output from array 12 is sent from terminal 17 to the address bus.

The instruction decoder 18 decodes the instruction supplied from the internal bus 10 and supplies the decoded result to the timing and control circuit 19. The instruction decoder 18 is capable of decoding macro instructions, which will be described later, in addition to normal machine language instructions such as data transfer instructions and performance/discharge instructions.

The accumulator 20 and the register 21 each store data from the internal data bus 10 and send out already stored data to the internal data bus 10. The smart logic circuit (ALLJ) 22 performs a sieve on the data supplied from the accumulator 20 and the register 21, and sends the sieve result data to the internal data bus 10.

The timing and controller 19 is supplied with the decoding results of instructions from the instruction decoder 18, and is also supplied with control signals such as clock signals and interrupts from the outside via the terminal 23, and outputs timing signals and control signals according to the decoding results. Generates signals to register array 12 within the CPU. Instruction decoder 18. Accumulator 20, register 21. It is supplied to ALLJ22 and the like, and also supplied to external circuits such as memory from the terminal 24.

Macro instructions include switch-to-macro (STM) instructions, next (NEXT) instructions, and call macros (CA).
LLM) instruction and return macro (RETM) instruction are provided.

The 87M instruction itself is a machine language instruction, stores the value of the program counter 15 in the second program counter 16, stores the contents of the address indicated by the second program counter 16 in the program counter 15, and writes the value of the program counter 15 to the second program counter 16. 15, and then instructs to increment the value of the second program counter 16 by [2].

The object program stores the start address of the macro instruction to be executed following the 87M instruction, and the 87M instruction causes the CPU to set the address where the start address of the macro instruction to be executed is stored in the second program counter 16. setting, and then switch from machine language instruction execution mode to macro instruction execution mode. Then, the macro instruction is executed, and the address storing the start address of the macro instruction to be executed next is set in the second program counter 16.

Note that the address is 2 bytes, and the program counter 15 and the like count in units of bytes.

The NEXT instruction itself is a machine language instruction, and the contents of the address indicated by the second program counter 16 are stored in the program counter 15 and the contents of the address indicated by the second program counter 16 are stored in the program counter 15.
5 and instructs to increment the value of the second program counter 16 by "2".

As a result, the CPU executes the next macro instruction and sets the second program counter 16 to the address storing the start address of the macro instruction to be executed next.

The CA11M instruction itself is a machine language instruction, which saves the value of the second program counter 16 to the stack indicated by the stack pointer 14, then stores the value of the program counter 15 in the second program counter 16, and saves the value of the second program counter 16 to the stack indicated by the stack pointer 14, and then stores the value of the program counter 15 in the second program counter 16, and The contents of the address indicated by the gram counter 16 are stored in the program counter 15, and the program counter 15
The program jumps to the address indicated by , and then instructs to increment the value of the second program counter 16 by "2". This allows the subroutine of the macro instruction to be called in the macro instruction execution mode.

The RETM instruction itself is the start address of the macro instruction, and the stack pointer 1 in the return macro instruction body.
The stack value indicated by 4 is returned to the second program counter 16, am of the addresses indicated by the second program counter 16 is stored in the program counter 15, jumps to the address indicated by the value, and then the second program The value of the counter 16 is incremented by "2". As a result, the CPU returns to the macro instruction execution mode from the macro instruction subroutine.

Next, the progress of the object program executed by the central processing unit of the present invention will be explained using FIG. The object program shown in FIG. 2 is stored on a memory connected to the CPU shown in FIG.

In FIG. 2, the CPU increments the value of the program counter 15 by "1" each time it executes each machine language instruction from address 8 to address B.

The STM instruction at address B+1 is executed and the CPU enters macro instruction execution mode. Address B+2 ~ Address C
In the figure, the macro address and the start address of the macro instruction to be displayed are stored.

The value of the start address (E) of the macro instruction at address B+1 is address E, and the CPU jumps to address E and sequentially executes the machine language instructions from address E to address F that constitute the macro instruction (E).

By executing the NEXT instruction at address F, the CPU executes the start address (G
) and directly jump to the address G indicated by CALLM.
The instruction is executed, and the CPU jumps to address M based on the start address (M) of the macro instruction at address G+1, and executes machine language instructions from address M to address N in order. Similarly, macro instructions whose start addresses are stored after address G+1 are executed.

The start address (R) of the macro instruction at address H indicates the RETM instruction at address R, and when the machine language instruction in the body of the return macro instruction at address R is executed, the CP
U jumps to address I and executes the machine language instruction indicated by the start address (I) of the macro instruction.

Similarly, when the NEXT instruction to the address that is the last machine language instruction that constitutes the start address (J) of the macro instruction at address C is executed, the CPU executes the NEXT instruction at address C.
Jump to +1. An address (C+2) indicating a return address in the machine language instruction mode is stored at address C+1, and the CPU sequentially executes the machine language instruction at address C+2 and subsequent machine language instructions.

By the way, when the macro instruction is for block transfer, this macro[1 instruction has the configuration shown in FIG. 3, for example. In the figure, the macro instruction (BTFR) at address J is:
Start address B of the macro instruction body that performs block transfer
Instruct TFR. This is followed by the transfer source address 8000. The transfer destination address AOOO and the number of transfer bytes 0010 are written as parameters, and the machine language instruction in the main body of the macro instruction is executed to transfer the transfer source address.

The transfer destination address and number of transfer bytes are read into the macro instruction body and block transfer is executed.

In this way, a series of procedures (routines) can be defined as macro instructions and executed independently of conventional subroutines.

When macro instructions are executed consecutively, the CPU jumps to the start address of the macro instruction in the direct method without returning to the main routine when the previous macro instruction ends, which is faster than when subroutines are executed continuously. Since only the start addresses of the macro instructions are sequentially written in the main routine, the number of bytes of the object program can be reduced, whereas JSR instruction codes are required for each subroutine.

Further, there is no need to provide an interceptor inside the CPLJ to execute macro instructions, and since no time is required to decode the interceptor, the macro instruction WORD of the FORTH language can also be executed at high speed.

Note that by stacking multiple macro instructions on the stack,
It is also possible to execute a subroutine of a macro instruction using an instruction similar to the CA11M instruction. In this case, the subroutine sequentially fetches macro instructions from the stack and executes them. In other words, by varying the stacked macro instructions, the content executed by the subroutine can be varied. Furthermore, since each macro instruction is expanded into multiple machine language instructions, many procedures can be stacked and passed to subroutines even if the stack has several levels.

〔Effect of the invention〕

As mentioned above, according to the central processing unit of the present invention, macro instructions can be defined and executed independently of subroutines, high-speed operation is possible, and the number of bytes of an object program is small, making it versatile, and extremely practical. Useful.

[Brief explanation of drawings]

FIG. 1 is a block system diagram of an embodiment of the central processing unit of the present invention, FIG. 2 is a diagram for explaining the progress of an object program executed by the central processing unit of the present invention, and FIG. 3 is a block diagram of an embodiment of the central processing unit of the present invention. FIG. 4 is a diagram for explaining the transfer macro instruction. FIG. 4 is a diagram for explaining the progress of an object program using conventional subroutines. In the drawing, 12 is a register φ array, 15 is a program counter, 16 is a second program counter, and 18 is an instruction decoder. -Ken's Microgrocery Pro, 77FJt
Figure m Figure 2

Claims (1)

[Scope of Claims] In a central processing unit that sequentially reads and decodes machine language instructions at addresses indicated by a program counter (15) and executes the machine language instructions, a macro instruction to be executed next in a macro instruction execution mode is executed. a second program counter (16) that indicates the address where the start address is stored; and a switch that indicates the start of the macro instruction execution mode and the setting of the address of the second program counter (16).
and an instruction decoder (18) that decodes all machine language instructions including at least a second macro instruction and a next instruction that instructs execution of the next macro instruction and setting of the address of the second program counter (16). , A central processing unit characterized by executing macro instructions defined by a set of multiple machine language instructions.