JPS6326889U - - Google Patents
Info
- Publication number
- JPS6326889U JPS6326889U JP11968486U JP11968486U JPS6326889U JP S6326889 U JPS6326889 U JP S6326889U JP 11968486 U JP11968486 U JP 11968486U JP 11968486 U JP11968486 U JP 11968486U JP S6326889 U JPS6326889 U JP S6326889U
- Authority
- JP
- Japan
- Prior art keywords
- display
- control circuit
- display control
- arithmetic unit
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Static Random-Access Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図は本考案の実施例を示す概略ブロツク図
、第２図は演算部と表示制御部との概略構成を示
すブロツク図、第３図は表示盤の制御を説明する
説明図、第４図本考案実施例で使用する表示素子
の構造を示す配線図、第５図ａ〜ｃは表示盤の表
示形態が複雑に変化した状態を示す参考図である
。
１……演算部、２……表示制御部、１１，１２
……ＣＰＵ、１２，２２……ＲＯＭ、１３，２３
……ＲＡＭ、１４，２４……Ｉ／Ｏ、３……垂直
制御回路、４……水平制御回路、５……表示盤、
６……電源、１５……デユアルポートＲＡＭ。
FIG. 1 is a schematic block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a calculation section and a display control section, FIG. 3 is an explanatory diagram illustrating control of the display panel, and FIG. Figures 5A to 5C are wiring diagrams showing the structure of the display element used in the embodiment of the present invention. Figures 5a to 5c are reference diagrams showing the state in which the display form of the display panel has changed in a complicated manner. 1... Arithmetic unit, 2... Display control unit, 11, 12
...CPU, 12,22...ROM, 13,23
...RAM, 14,24...I/O, 3...Vertical control circuit, 4...Horizontal control circuit, 5...Display panel,
6...Power supply, 15...Dual port RAM.
Claims (1)
１４から成る演算部１と、ＣＰＵ２１，ＲＯＭ２
２，ＲＡＭ２３，Ｉ／Ｏ２４とから成る表示制御
部２と、該表示制御部２によつて表示制御される
垂直制御回路３及び水平制御回路４と、表示盤５
と電源６とから成り、且つ前記演算部１と前記表
示制御部２との接続にデユアルポートＲＡＭ１５
を前記演算部１に具備したことを特徴とするカラ
ー電光表示装置。 CPU11, ROM12, RAM13, I/O
14, a CPU 21, and a ROM 2.
2, a display control section 2 consisting of a RAM 23 and an I/O 24, a vertical control circuit 3 and a horizontal control circuit 4 whose display is controlled by the display control section 2, and a display panel 5.
and a power supply 6, and a dual port RAM 15 is connected to the arithmetic unit 1 and the display control unit 2.
A color electronic display device characterized in that the arithmetic unit 1 is provided with the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11968486U JPS6326889U (en) | 1986-08-04 | 1986-08-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11968486U JPS6326889U (en) | 1986-08-04 | 1986-08-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6326889U true JPS6326889U (en) | 1988-02-22 |
Family
ID=31007285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11968486U Pending JPS6326889U (en) | 1986-08-04 | 1986-08-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6326889U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072020A (en) * | 1983-09-29 | 1985-04-24 | Nec Corp | Dual port memory circuit |
| JPS617877A (en) * | 1984-06-22 | 1986-01-14 | 三菱電機株式会社 | Character pattern expander for crt |
-
1986
- 1986-08-04 JP JP11968486U patent/JPS6326889U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072020A (en) * | 1983-09-29 | 1985-04-24 | Nec Corp | Dual port memory circuit |
| JPS617877A (en) * | 1984-06-22 | 1986-01-14 | 三菱電機株式会社 | Character pattern expander for crt |