JPS63262766A - Decentralized picture data display control system - Google Patents

Abstract

PURPOSE:To dynamically set an assigned area and to divide and control a picture in a real time by providing a means for storing the assigned area information of a cell and a means for determining the assigned area based on the contents of this storage in the respective cells. CONSTITUTION:Based on an instruction from a host computer 13, the assigned area information of respective processor elements (cell) 10 is set to an assigned area information storing circuit 24 by a processor 12. Based on the contents of this setting, the assigned area of its own cell 10 is determined by an assigned area decision circuit 25 and based on the output signal of the circuit 25, the address of a picture memory 11 for storing picture data relating to this assigned area is generated in a picture memory address generating circuit 23. The competition of an access to the memory 11 of the processor 11 for processing the picture data relating to this assigned area and an access to the memory 11 by the address from the circuit 23 for reading the displayed picture data is adjusted by an access competition adjusting circuit 21.

Description

[Detailed description of the invention] 〔overview〕 When generating images using multiprocessors.

In order to speed up image generation and distribute the load, each processor element (hereinafter referred to as a cell)

A circuit that stores and determines its own block area in an image based on a control signal given from the outside, a circuit that generates an address for one image memory, and a circuit that allows the processor to access the image memory. By having this, it is possible to perform image division control in real time and dynamically change the area in charge of each cell.

[Industrial application field]

The present invention relates to a system that generates images using a multiprocessor, and in particular to a distributed image data display control method that distributes the area in charge of one cell over two images as uniformly as possible and combines the images into one when two images are displayed. It is something.

Recently, images have been generated using computers in movies and the like. Image generation like this.

Since it takes a long calculation time to draw one picture and it is necessary to create many pictures, there is a tendency to improve throughput through parallel processing.

How to efficiently generate images using parallel processing.

It is necessary to equalize the load on all cells as much as possible. Furthermore, it is necessary to be able to display the generated image data immediately.

[Traditional techniques fJ, Te]

FIG. 8 is an explanatory diagram of the conventional system.

Many attempts have been made to generate images using multiprocessors (References: Nishimura et al., rLINKS1: Computer Graphic System, Information Processing Society of Japan, Microcomputer Research Materials, November 1982). In many of these systems, image data generated by each cell is once collected in a frame buffer and then displayed. In such a system, bus contention is likely to occur when writing each cell to the frame buffer, so the time required to collect five image data into the frame buffer becomes a bottleneck, making it difficult to meet the demand for real-time display.

For this reason, a system has been proposed in which every cell has an image memory that can be read out in real time, as disclosed in, for example, Japanese Patent Laid-Open No. 59-172064. This kind of traditional image processing system.

For example, as shown in FIG. 8(a), each cell C1l to Cn
m is connected to the host computer 13 via the command bus 14, and connected to the video 117)0-ra 17 via the video bus 15. In addition, each cell CI
1 to Cnm have a processor that processes one image data and an image memory that can be read out in real time via the video bus 15.

FIG. 8(b) shows each cell C11 to C for two images 8o.
A simplified example is shown for regions R11 to Rnm, which are respectively in charge of nm. In a certain cell, region R1
A signal indicating that j is the area in charge of that cell is generated by an area signal SH in the horizontal direction and an area signal SV in the vertical direction.

That is, this assigned area signal is stored in area tables 83 and 84 as shown in FIG. 8(c), respectively, in the horizontal direction and
Memorize the wind pattern in the vertical direction,
These area tables 83 and 84 are processed by a horizontal scan counter 81 and a vertical scan counter 82, respectively.
and the AND circuit 85 on its output.
It is generated by taking the logical product.

Note that if the number of pixels in the horizontal direction is h, the area table 83 has a size of h bits, and the area table 84 has a size of h bits.
If the number of pixels in the vertical direction is V.

■Has a bit size. Horizontal scan counter 8
1. The vertical scan counters 82 are each operated by a horizontal synchronization signal r(D) and a vertical synchronization signal VD from the video controller.

[Problem that the invention seeks to solve]

In the conventional method as shown in FIG. 8, the area of the image that each cell is responsible for is identified using an area table provided for each cell.

There is a problem in that it takes an hour if the area in charge needs to be rewritten due to image movement or the like. Therefore, the assigned area is determined by a substantially fixed window pattern, such that each cell is assigned to an area alternately, for example, one pixel at a time.

However, in order to average the load on each cell as much as possible and speed up the generation of one image, it is desirable to be able to dynamically and quickly change the assigned area depending on the display contents of one image.

An object of the present invention is to solve the above-mentioned problems and provide a means for controlling division of nine images in real time.

c.Means for solving problems] FIG. 1 shows an example of the basic configuration of the present invention.

FIG. 1(A) shows an example of the overall system configuration of 9 of the present invention, in which 10 is a cell, 11 is an image memory (VRAM) for storing distributed image data, and 12 is for processing distributed image data. processor.

13 is the host computer, 14 is the host total 1:1. 15 is a video bus to which image data read from each image memory 11 is output; 16 is a control bus for horizontal synchronization signals, vertical synchronization signals, 1 image clock, etc.; 17 is the video controller, 1
8 is a display.

FIG. 1(b) shows an example of the internal configuration of each cell 10, with reference numeral 20 an image memory control circuit, 21 an access conflict arbitration circuit for the processor 12 to access the image memory, and 22 an assigned area signal and A window controller that generates image memory addresses; 23 an image memory address generation circuit that generates image memory addresses; and 24 an assigned area storage circuit that stores assigned area information divided into blocks.

25 is a responsible area determination circuit for determining the own responsible area;
6 is a selector, 27 is a ROM that stores instructions and the like to be executed by the processor 12, and 28 is a RAM.

29 is a host interface connecting the command bus 14 and the internal bus, 30 is an address bus, and 31 is a data bus.

Processor 12 via data bus 31.

An instruction is fetched from the ROM 27 specified by the address bus 30 and executed. Commands from the host computer 13 are notified via the host interface 29.

The assigned area storage circuit 24 stores information regarding the blocked assigned area that the own cell 10 is assigned to. The responsible area determination circuit 25 is a circuit that determines its own responsible area based on the contents of the responsible area storage circuit 24, and outputs a responsible area signal indicating that it is the responsible area. The image memory address generation circuit 23 generates an address for one image memory 11 based on the area signal in its duty.

The access conflict arbitration circuit 21 is a circuit that performs control to make access by the processor 12 to the one-image memory 11 wait while display data is being read from the one-image memory 11. The selector 26 is.

Based on the output of the access contention arbitration circuit 21, the processor 1
Image memory address generation circuit 23 for reading the address of the image memory 11 to be accessed by No. 2 and the display data of No. 1
The address where the error occurred is switched.

The data in the image memory 11 read out by the address generated by the image memory address generation circuit 23 is read out by the assigned area signal, for example, via an open collector buffer.
It is sent to video bus 15.

[Effect]

The processor 12 performs host calculation [13] according to instructions from the host computer 13 to calculate 1 display start position information 2 display end position information.

When the minimum necessary area information such as block information is set in the area storage circuit 24, the area determination circuit 25 determines the area based on the settings, and the access contention arbitration circuit 21 and the image memory address The operation of the generating circuit 23 is controlled. Therefore, the PM can simply and quickly dynamically set the area in which he/she is in charge, and it is possible to control the division of two images in real time.

〔Example〕

FIG. 2 is an explanatory diagram of the coverage area of one cell according to an embodiment of the present invention, FIG. 3 is an example of a circuit of a part of the window controller shown in FIG. 1, and FIG. 4 is an image memory address shown in FIG. 1. Examples of generation circuits, FIG. 5 shows a time chart of a window controller, FIG. 6 shows an example of the access contention arbitration circuit shown in FIG. 1, and FIG. 7 shows a time chart of the access contention arbitration circuit shown in the sixth leap diagram.

In the three image data 35 as shown in FIG.

One cell consists of one sub-block, for example, SBI, SB2, .
..., in charge of the discrete block-like areas of SB6. Furthermore, the numerical values in each sub-block are as follows.

It represents the address of the corresponding image memory. Each cell is configured to sequentially store image data for the portion it is in charge of.

Note that DSX and DSY shown in FIG. 2 are the X direction of the display area 36 in the entire image data 35.

The size in the Y direction is shown, and DOFSX and DOFSY show the starting relative position of one display area 36.

5BSX and 5BSY indicate the size of the subblock in the X and Y directions, and ○FSX and 0FSY indicate the starting relative position of the first subblock. BSX and BSY are block sizes and indicate the distance between one subblock and the primary subblock. aX and a7 indicate the offset from the first sub-block to the display area.

Next, parameter settings for the window controller 22 shown in FIG. 1 will be explained using the assigned area shown in FIG. 2 as an example.

In this example, one cell covers an area of 3 pixels x 3 pixels.
Responsible for areas arranged every pixel, and multiple cells (9x3
= 27 cells), one image data is stored.

Here, by command from the host computer.

Of the entire image, an image of size DSXXDSY starting from (DOFSX, DOFSY) is displayed on the screen (
Consider displaying from the position (STX, 5TY). Since the processing is similar in the horizontal direction and the vertical direction, the horizontal direction will be explained as an example.

+11 0 F S X > D OF S X (7
), your display start position is X=STX+DOFSX
-OFSX. Therefore, the window controller 22
The parameters for are.

■ Display area start position xpws=x ■Display area end position XPWE=X+DSX ■　Block initial value XBIR=0 ■ Block size XBSR=BSX=8 (To control as a 9-decimal counter.

9-1 cents) ■ Sub-block size X5BSR=SBSX-2 (For 3 clock width pulse control.

3-1 cents) ■Number of pixels assigned to you in one screen LSR=9 ■Number of pixels in one frame FSR=54 ■ Start address of 1 frame FBA-0 becomes.

When +21 0 F S X ≦DOF S Therefore, the make-up of the window controller 22 is as follows.

■ xpws=x ■ XPWE=X+DSX ■ XBIR-ax mod BSX=1■ XBS
R=BSX=8 ■ X5BSR-3BSX=2 ■ LSR=9 ■ FSR=54' ■ FBA-a yXLsR+a x=10.

(3) When OFSX≦DOFSX and (axmod BSX)≧5BSX, your own display start position starts from the middle of your own area and from the beginning of the block. Therefore, the process is the same as the case (2) above, except that the block initial value XBIR becomes 0.

By dynamically changing these parameters ■～■,
It is possible to divide the image in various ways, such as in a line shape or in a block shape, and any rectangular area of the image data divided and stored in this way can be displayed in real time.

FIG. 3 shows an example of a part of the circuit of the window controller 22 shown in FIG. 1, where 40X is a horizontal scan counter, 40Y is a vertical scan counter, 41X,
41Y is a display area start position register, 42X and 42Y are display area end position registers, 43X and 43Y are block initial value registers, and 44X and 44Y are block size registers.

45X and 45Y are sub-block size registers.

46X, 46Y are block size counters, 47X ~
50X, 47Y to 50Y are comparators, 51X.

51Y and 52 represent AND circuits.

The generation of a horizontal wind pattern will be described below, but the same applies to the vertical direction.

The processor sets the above parameter (2) in the 1 display area start position register 41X, and sets the above parameter (2) in the 2 display area end position register 42X. The above parameter (2) is set in the block initial value register 43X. The above parameter (2) is set in the block size register 44X, and the above parameter (2) is set in the sub-block size register 45X. These registers correspond to the dedicated tilting memory circuit 24 shown in FIG.

The horizontal scan counter 40X is operated by an externally applied clock and indicates the horizontal position of one image. This output and 1 display area start position.

A signal indicating the display area of two images is outputted via the AND circuit 51X by comparison with the display area end position.

At the start of the display area, the value of the block initial value register 43X is loaded into the block size counter 46X.
The block size counter is 46X.

It is counted up by the same clock as the horizontal scan counter 40X. As a result, if one display area starts from the middle of a block, the block size counter 4
6X will start counting from its initial value aX.

The value of block size counter 46X is constantly compared with the contents of block size register 44X and sub-block size register 45X. Block size counter 46X
When the value of block size register 44X becomes equal to the value of block size register 44X, block size counter 46X is cleared.

The assigned area signal is output only when the value of block size counter 46X is smaller than the value of sub-block size register 45X.

In the vertical direction, the responsible area is determined in the same way.
The AND circuit 52 outputs an assigned area signal based on logical product in the horizontal direction and the vertical direction.

The image memory address generation circuit 23 shown in FIG. 1 is configured as shown in FIG. 4, for example. In Figure 4, 6
0 is a frame base address register, 61 is a pixel address counter, 62 is a line address register, 6
3 is the frame address register, 64 is the line size register, 65 is the frame size register, 66.67
is a selector, 68 is a CPU access address register,
69 represents an adder.

The frame base address register 60 is set with the first address of nine image data, and the line size register 60 is set with the first address of nine image data.
4. The frame size register 65 stores the number of pixels in one line and the number of pixels in one frame, which are handled by the own cell.

At the beginning of the first frame, the contents of the frame base address register 60 are changed to the pixel address counter 61 and
and line address register 62.

The frame address register 63 is loaded.

The contents of the pixel address counter 61 are output as addresses for accessing the 8-image memory and incremented by the assigned area signal output from the window controller.

At the beginning of each line, the contents of the line address register 62 plus the contents of the line size register 64 are loaded into the 8-pixel address counter 61 and the line address register 62.

It is now ready to display the next line.

When the next frame is to be displayed at the end of one frame, the sum of the contents of the frame address register 63 and the contents of the frame size register 65 is loaded into the pixel address counter 61 and the frame address register 63.

It is now ready to display the next frame.

FIG. 5 is a time chart showing the operation of the circuit shown in FIGS. 3 and 4. FIG.

The output of the AND circuit 51X shown in FIG. 3 is as shown in FIG. 5(a).
This is a signal indicating the display area like this. The output of the comparator 50X becomes a signal indicating the position of the sub-block as shown in FIG. 5(b). Now, suppose we are inside a buburonok that also shows about the vertical direction.

The output of the AND circuit 52 shown in FIG. 3 becomes a signal indicating the assigned area as shown in FIG. 5(e). With such a signal, the image memory (VRAM) address, which is the output of the selector 26 shown in FIG. 4, is as follows.

The result will be as shown in FIG. 5(d). Note that here, in order to simplify the diagram, the sub-block size is set to 2 pixels.

5 Regarding the operation of the window controller 22 A more detailed explanation is as follows.

Image data is the pixel clock XCLOCK and line clock YCLOCK sent from the video controller.
, horizontal clear signal XCLEAR, vertical clear signal YCL
Input/output is controlled by the EAR's four-tree control bus. The horizontal scan counter 40X shown in FIG. 3 counts XCLOCK and is cleared by XCLEAR. The vertical scan counter 40Y is YCLOC.
K is counted and cleared by YCLEAR.

Also for controlling the start and end of 0 image input/output.

It has a start signal and a stop signal. These signals are
Wired OR logic is performed between all cells.

The results can be recognized by individual cells.

Input/output is started or stopped when all cells output start or stop. This signal can be masked. When masked, input/output starts regardless of the state of other cells. Furthermore, it is possible to have an animation @g for sequentially inputting and outputting a plurality of images, and in this case, when two-image inputting and outputting starts, frames are sequentially switched.

The access contention arbitration circuit 21 shown in FIG.
It is as shown in the figure. FIG. 7 shows its operation time chart. In FIG.

70 to 73 are flip-flops, 74 is an inverter, and 75 is an AND circuit.

The image memory consists of 5 wind controllers and processors (
It may be accessed by both CPUs at the same time. In this case, the window controller side is arbitrated preferentially. When the assigned area signal (b) from the window controller is "H", access by the processor (CPU) is not possible.

When it is 'L', access is possible. When access is disabled, the output (C) of the AND circuit 75 is @L, and the output (d) of the flip-flop 73 is 'H'.

Therefore, the flip-flop 70 is set at the rise of the CPU's request to access the image memory.
A wait request signal wait is output to the CPU.

When the assigned area signal (b) becomes "L" and the CPU access is enabled, the output of the AND circuit 75 becomes "H", so the image memory access signal is output from the flip-flop 72 in synchronization with the 2nd clock. Output. At this time, C
Flip-flop 71 holding the PU access request is cleared.

Furthermore, since the output of the flip-flop 73 becomes "L" with the primary clock, the flip-flop 7° is cleared and the CPU wait is released.

The commands from the host computer 13 shown in FIG. 1(a) are broadcast to all cells. A command consists of a command part and a parameter part. Below is an example of the command.

■ Window controller initialization vinito () This is a command to initialize the window controller. This allows you to recognize the total number of cells and your own cell address.

■ Image memory acquisition vgetgr (frame, xs, ys) xsxys
For the image frame, it is declared that the image memory for frame is to be used.

■ Image division specification vmdblk (ofsx, ofsy, bsx.

b s y, s b s x, s b s y
) orsx, ofsy, block size is b
sx, bsy, sub-block size is 5bsx, 5bs
Specify to be in charge of the area divided into y.

■ Display position and size specification vmwind (xs t, 75 t, XS, ys) xs, y starting from xst, yst position of display
One image data is displayed in an area of size s.

■ Writing and reading images vwtg (x, y, COL) vrdg (x, y, COL) Writes image data to the specified position. Also, the image data at the specified position is read out. COL is color information.

In addition, there are various commands related to drawing a circle, a straight line, an ellipse, a polygon, three filled characters, etc. By passing these commands through the host interface as variable length buckets.

Transmission and reception are performed.

〔Effect of the invention〕

As explained above, according to the present invention, by changing the parameters related to the assigned area, it is possible to take various image divisions such as a line shape or a prong shape. The rectangular area of
It can be displayed immediately.

[Brief explanation of drawings]

FIG. 1 is an example of the basic configuration of the present invention, FIG. 2 is an explanatory diagram of the coverage area of one cell according to an embodiment of the present invention, and FIG. 3 is an example of a part of the circuit of the window controller shown in FIG. Figure 4 is the first
An example of the image memory address generation circuit shown in the figure, FIG. 5 is a time chart of a window controller, FIG. 6 is an example of the access conflict arbitration circuit shown in FIG. 1, and FIG. 7 is a time chart of the access conflict arbitration circuit shown in FIG. The chart shown in FIG. 8 is an explanatory diagram of the conventional method. In the figure, 10 is a cell, 11 is an image memory, 12 is a processor, 13 is a host computer, 14 is a command bus, 15 is a video bus, 16 is a control bus, 17 is a video controller, and 18 is a display. 20 is an image memory control circuit, 21 is an access conflict arbitration circuit, 22 is a window controller, 23 is an image memory address generation circuit, 24 is an assigned area storage circuit, 25 is an assigned area determination circuit, 26 is a selector, 27 is a ROM, 28 is a RAM, 29 is a host interface, 30 is an address bus, and 31 is a data bus.

Claims (1)

[Claims] A processor that processes image data related to the area in charge;
A system comprising a plurality of cells (10) each including an image memory storing distributed image data corresponding to the processor, each cell (10)
In the distributed image data display control method in which image data stored in a distributed manner in the image memory held by the cell is read out and displayed as one image data, each cell (10) is An assigned area storage circuit (24) that stores area information through dynamic settings, and an assigned area determination circuit (25) that determines the assigned area in the image based on the output of the assigned area storage circuit (24). , an image memory address generation circuit (23) that generates the address of the image memory that stores the image data in charge;
and access of the processor to the image memory,
The access conflict arbitration circuit (21) arbitrates conflicts with read access of the image data to be displayed, and the output of the image data to be displayed is controlled by the output of the responsible area determination circuit (25). Features a distributed image data display control method.