JPS63261744A - solid-state imaging device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] This invention is based on the potency due to the accumulation of photo-generated charges.

CM D (Charg
eModulation Device) The present invention relates to a solid-state imaging device comprising pixels using a light receiving element as a photoelectric conversion element.

[Conventional technology]

Conventionally, COD and MO3-type imaging elements have been known as solid-state imaging devices, but in all of these elements, the photo-generated charges accumulated in the photodiode are transferred directly to the output section and read directly as signal charges. It is configured. Therefore, in these devices, miniaturization and
This has the problem that the S/N ratio of the output signal deteriorates as the number of pixels increases.

In response to this, the present inventors previously proposed a CMD light receiving element that has an amplification function for each pixel and is capable of non-destructive readout. For detailed technical details of this CMD photodetector, please refer to the Inter-nationa held in 1986.
l Electron Device Meeting
(I ED M) proceedings, pages 353-356@
A NEW MOS I gate AGESENSOR0
PERATING IN A N0N-DESTRUC
IVE READOllTMODE”.

A planar structure and a cross-sectional structure of a configuration example of a solid-state imaging device using such a CMD light-receiving element as a pixel are shown in FIG. 5 and (B). In the figure, 101 is a p-substrate, 102 is a channel layer made of an n-epitaxial layer formed on the substrate 101, 103 is a source region made of an n0 diffusion layer, 1
04 is a shallow drain region consisting of a shallow n diffusion layer; 10
5 is a deep drain region made of a deep n' diffusion layer and functions as an isolation region; 106 is an insulating film; 107 is a gate electrode formed to surround the source region 103; 108 is a common gate line; 109 is a common source line; 110
1 is a wiring made of a metal thin film connecting each gate electrode 107 and the gate line 108, and 111 is a source electrode. And the source region 103 of the CMD light receiving element which becomes a pixel. Gate electrode 107. The shallow and deep drain regions 104 and 105 have a planar structure arranged concentrically, the gate electrodes 107 of each pixel are horizontally connected by a common gate line 108, and the source region 103 is connected by a common source line 109. connected vertically.

The CMD light-receiving element during light reception and readout operates as a bulk channel MO3) transistor, and the photo-generated holes are accumulated directly under the gate electrode 107, forming an inversion layer. When this inversion layer is not formed, a potential barrier is formed in the bulk channel due to the negative potential applied to the gate electrode 107, and no electron current flows from the source region 103 to the drain regions 104 and 105.
On the other hand, when an inversion layer is formed by light irradiation, the height of the potential barrier in the bulk channel is lowered, and an electron current modulated in accordance with the holes in the inversion layer flows.

Therefore, the gate line 108 is connected to the vertical scanning circuit, the source line 109 is connected to the horizontal scanning circuit via the MOS selection switch, and the horizontal scanning circuit selects the pixels connected to the gate line selected by the vertical scanning circuit. The amount of incident light can be detected as a change in voltage by passing the source current of the pixels in the selected column to the load via the video line.

[Problem that the invention seeks to solve]

By the way, in a solid-state imaging device using a conventional CMD light receiving element as a pixel, a large number of CMDs constituting each pixel
Each gate electrode of the light receiving element is configured to be connected to a gate line via a gate contact.

Therefore, the area of the gate contact portion in the entire solid-state imaging device becomes extremely large, making it difficult to increase the pixel density, and in cases where a small chip size is required, it becomes impossible to obtain high-quality images. There was a problem with it being put away.

The present invention has been made in order to solve the above-mentioned problems in solid-state imaging devices that use conventional CMD light receiving elements as pixels. CM that enables
An object of the present invention is to provide a solid-state imaging device using a D light receiving element.

[Means and operations for solving the problems] In order to solve the above problems, the present invention is configured such that each gate electrode of a plurality of adjacent CMD light receiving elements is connected to a gate line by one gate contact. It is something to do.

With this configuration, the area of the gate contact portion can be reduced, making it possible to reduce the chip size and increase the pixel density.
It becomes possible to easily obtain a solid-state imaging device using a CMD light-receiving element that is small and has high image quality.

Next, the present invention will be explained in more detail based on the conceptual diagram showing the basic configuration of the present invention shown in FIG. 1. From each gate electrode 3-1.3-2 formed so as to surround the source region 2 of the element, an extension portion 3-11+ 3-*a
The cross joint portion 4 is integrally formed by extending diagonally so as to intersect with each other.

The gate electrode cross-coupling section 4 is connected to a common gate line 5 arranged between horizontal pixel columns through - gate contacts 6. In FIG. 1, 7 is a shallow drain region, and 8 is a deep drain region forming an isolation region. By connecting each gate electrode of two pixels to the gate line through one gate contact in this manner, the area of the gate contact portion can be reduced to 1/2.

〔Example〕

Examples will be described below. FIG. 2 is a leap diagram showing the planar structure of an embodiment of the solid-state imaging device according to the present invention. In the figure, 1-1.1-z is a pixel consisting of adjacent CMD light receiving elements arranged in the horizontal direction, 2 is a source region, and 3-63-z is each source region 2 of each pixel 1-1+It. A gate electrode is formed of a first polysilicon so as to surround the gate electrode, and extension parts 3-1m+3-za are extended diagonally from the gate electrode 3-1. A connecting portion 4 is formed. Reference numeral 5 denotes a second gate electrode, which is disposed so as to pass over the gate electrode coupling portion 4 between the pixel columns arranged in the horizontal direction.
A gate line 5 is formed of polysilicon, and the gate electrode coupling portion 4 is connected to the gate line 5 through one gate contact 6. 7 is a shallow drain region formed by a shallow diffusion region, and 8 is a deep drain region formed by a deep diffusion region, which constitute an isolation region between each pixel.

A source line 9 is arranged so as to pass over each source region 2 of each pixel arranged in the vertical direction, and is connected to the source region 2 of each pixel by a source contact 10.

Reference numeral 11 denotes a drain line, which is arranged vertically between pixels where the gate electrode coupling portion 4 is not arranged, and is connected to the deep drain region 8 via the drain contact 2.

Two adjacent pixels arranged horizontally as described above 1. ．． 1. Each gate electrode 3-1. 3-z, 1
Since the gate electrodes of each pixel are connected to the gate line 5 through the gate contacts 4, the area of the gate contact portion is smaller than that of the conventional case where the gate electrode of each pixel is connected to the gate line through the gate contact. You can halve the comparison. Further, since the gate contact portion is arranged diagonally between each pixel, the source line can be arranged across directly above the pixels as in this embodiment. Therefore, the area corresponding to the source line when arranged between vertical pixel columns can be reduced. Furthermore, by arranging the source line across the center of the pixel, the drain line can be arranged at the conventional source line arrangement position. Therefore, the drain contact can be placed near each pixel without increasing the area, and the potential of the common drain of each pixel can be stabilized.

FIG. 3 is a diagram showing a planar structure of a modification of the embodiment shown in FIG. 2. In this modification, the gate line 5' is formed using a metal thin film to reduce the wiring width, and the shape of the gate contact 6' and the gate line 5' are changed accordingly.
By making the shape of the gate contact portion into a diamond shape as shown in the figure, the area of the gate contact portion can be further reduced, and the density of pixels can be increased.

FIG. 4 is a diagram showing a planar structure of another embodiment of the present invention, in which constituent members that are the same as or equivalent to those of the embodiment shown in FIG. 2 are denoted by the same reference numerals.

In this embodiment, each gate electrode of four pixels is commonly connected to a gate line using one gate contact. That is, four pixels 1-1n 14+ 1-sr 1- adjacent in the horizontal and vertical directions
Each gate electrode 3-1.3 of the CMD light receiving element constituting 4
-z, 3-3. From 3-4, extension 3-+□, respectively
3-zm+ 3-3m+ 3-am are made to protrude diagonally so as to intersect, thereby forming a common joint portion 4'.

The common coupling portions 4 to ′ of the gate electrodes are connected to the gate lines 5 arranged every two pixel columns between the horizontal pixel columns via one gate contact 6, and the four gate electrodes 3 -,. 3-1 3-:l+3-4 are configured to be commonly connected to the gate line 5 by one gate contact 6.

9-1.9-1 are two source lines arranged vertically across the source region 2 of each pixel, and each source line 9-+, 9-z has a source contact 10-.
+, 10-z, the source regions 2 are alternately connected every other pixel.

In this way, four pixels 1-
+, 1-t, 1-3. 11 each gate electrode 3-1゜3
-t, 3-x, 3-a are configured to be connected to the gate line 5 with one gate contact 6,
The number of gate lines in the entire solid-state imaging device can be reduced to half of the conventional number. In this case, two pixel columns arranged in the horizontal direction are selected at the same time, so these two
In order to separate and read out each pixel arranged horizontally in a column, two source lines are required for one pixel column arranged vertically, as shown in the figure.
By slightly sacrificing the light-receiving area, it is possible to significantly reduce the chip area.

Further, in this case, if the two source lines are arranged so as to overlap each other on one side using a multilayer wiring method, the reduction in the light receiving area can be minimized.

In the embodiment shown in FIG. 2, a deep drain region is provided between each pixel arranged in the horizontal direction, but this deep drain region is not provided in the modification shown in FIG. It can be removed in the same manner as in the embodiment shown in Part 4, and thereby the chip area can be further reduced.

〔Effect of the invention〕

As explained above based on the embodiments, according to the present invention, one gate contact is used. Since each gate electrode of several CMD light-receiving elements is configured to be connected to the gate line, it is possible to reduce the area of the gate contact part, and it is possible to reduce the chip size and increase the pixel density. be able to.

In addition, by configuring multiple gate electrodes to be connected to the gate line through a common gate contact, the degree of freedom in arranging source lines, etc. is increased, and more suitable wiring is possible. A solid-state imaging device with high image quality can be obtained.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram showing the basic configuration of a solid-state imaging device according to the present invention, FIG. 2 is a diagram showing a planar structure of an embodiment of the present invention, and FIG. 3 is an embodiment shown in FIG. 2. FIG. 4 is a diagram showing a planar structure of another embodiment of the present invention, and FIGS. FIG. 2 is a diagram showing a planar configuration and a cross section of In the figure, 1-11 1-2+ 1-s, 1-4 is a pixel consisting of a CMD light receiving element, 2 is a source head mounted, 3-
1゜3-2.3-s, 3-- is the gate electrode, 4.4' is the gate electrode coupling part, 5, 5' is the gate line, 6.6'
is the gate contact, 7 is the shallow drain region, 8 is the deep drain region, 9.9-+, 9-z are the source lines, 1
0.10-, , 10-z are source contacts, 11 is a drain line, and 12 is a drain contact. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 2 Figure 3 Figure 5 (A) (B)

Claims (1)

[Claims] Pixels using CMD light receiving elements with an internal amplification function as photoelectric conversion elements are arranged in a matrix, and a gate line is provided to commonly connect each gate electrode of each CMD light receiving element arranged in one direction. A solid-state imaging device characterized in that each gate electrode of a plurality of adjacent CMD light receiving elements is connected to a gate line by one gate contact.