JPS63261577A - Digital type phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To realize the actuation of a digital type phase synchronizing circuit with a sampling frequency of >=2 times as high as the frequency that is decided by the delay time of a phase locked loop, by calculating an average phase of the prescribed sampling points set at the plural adjacent sampling intervals and correcting the phase of the phase locked loop for each sampling point based on said average phase. CONSTITUTION:The average phases are processed in parallel at plural intervals based on the data on >=3 sampling points and the phase of a phase locked loop circuit is corrected at each sampling point. The average phase of plural intervals among those sampling points is calculated by subtracting the sum of the absolute values of the sampling data on both ends of an interval where a zero cross exists from the average value obtained by averaging the absolute value of the sampling data on one of said both ends. For calculation of the average phase among plural intervals, the addition is performed by the simple parallel processes and the pipeline processing is possible owing to the absence of a feedback loop. Thus said average phase can be calculated at a high speed. Furthermore it is possible to handle a frequency higher than that decided by the delay time of a phase locked loop.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is applicable to magnetic recording and reproducing devices and information transmission devices,
The present invention relates to a digital phase synchronization circuit necessary for reproducing and receiving digital signals.

(Prior Art) In a magnetic recording and reproducing device using a magnetic tape, a magnetic disk, etc. as a recording medium, in order to record a digital signal and identify and reproduce the original digital signal from the read signal, it is necessary to identify and reproduce the original digital signal from the read signal. A phase-locked circuit is required to extract a clock signal with a frequency equal to the bit rate. Conventionally,
An analog type phase-locked circuit using a voltage-controlled oscillator was used as a phase-locked circuit in a magnetic recording/reproducing device. However, for magnetic recording devices with low recording data rates such as multi-track digital audio chip recorders, digital phase synchronization circuits such as the one proposed in JP-A-59-92410 are not suitable for IC implementation. , Sugita et al. [On a method of data detection in fixed head digital tape recorders] (IEICE technical report EA82-59, pages 33-40
A similar phase synchronization circuit is also described in "Fixed Head Type Digital Audio Tape Recorder" by Daiki et al. (IEICE technical report EA86-9, pages 41 to 48).

Fig. 5 is a schematic block diagram of a conventional digital phase synchronization circuit proposed in Japanese Patent Application Laid-Open No. 59-92410;
The figure is a waveform diagram for explaining FIG. 5. In FIG. 5, an input terminal 300 receives a reproduced signal, which is a signal read out by a reproducing head in a magnetic recording and reproducing apparatus, amplified by a preamplifier, and whose waveform is equalized by an equalization circuit.

When the channel data rate of the signal to be recorded and reproduced is f bits/see, it is sufficient that the sampling frequency is 2 fHz or more, and as shown in Fig. 5, the reproduced signal is
The sampling frequency of the A/D converter 301 that performs /D conversion is twice the channel data rate from the sampling clock generator 302. The reproduced signal R applied to the input terminal 300 is converted into digital data S, S2...S by the A/D conversion 301 as shown in FIG.
i... is converted. These data are each M
(M is a positive integer) Although this is bit parallel data, it is shown as a single line because it is complicated in the figure. The digital data is applied to a D flip-flop 303, a phase calculation circuit 304, and a zero cross detection circuit 305, and is delayed by one sampling period by the D flip-flop 303. The output of the D flip-flop 303 is the phase calculation circuit 30.
4 and zero cross detection circuit 305. The phase calculation circuit 304 calculates the value of S from the zero cross point from the input data S and S when there is a zero cross point between the sampling point of the data S1 and the sampling point of the data S. In a circuit that calculates the phase of a sample point, when each phase of 1+1 360° is expressed by 2n, the points S 2 and S 2 are linearly approximated as shown in FIG. 6 to perform calculations for one country. Here Is + and Is l are i
I11 Represents the absolute value of data S , S . The zero cross country I detection circuit 305 is a circuit that detects the existence of a zero cross between adjacent sample points, and detects the case where data Si and S have different signs. The outputs of the it sum calculation circuit 3'04 and the zero cross detection circuit 305 are respectively applied to D flip-flops 306 and 307 and latched. θ1 of equation (1), which is the output of the D flip-flop 306, is added to the coefficient K(
However, it is multiplied by 0<K≦1). That is, coefficient unit 3
The output of 10 is K(θ1−θ.). The output of the coefficient unit 310 is added to one input of the AND gate 311, and D
It is opened and closed by the output of flip-flop 307. That is, when a zero cross is detected, θ expressed by equation (1) represents the phase of S and is 11+, so the output K (θ1−θ.) of the coefficient multiplier 310 calculated by this θl is sent to the adder 312. When the AND gate 311 is opened and no zero cross is detected, (
Since θl calculated by equation 1) does not represent the phase of S, the ant gate 311 is closed and the adder 312 is controlled to add 0. Therefore, the subtraction circuit 308. The coefficient unit 310 and the AND gate 311 form a phase comparator and a loop filter in a phase locked circuit.

Adder 312 connects the output of AND gate 311 and adder 30
The outputs of D flip-flop 313 are added together and inputted to D flip-flop 313, and the output of D flip-flop 313 is added to adder 309. The other input of adder 309 is 2 generator 3.
Certain data of 2 has been added from 14. Adder 3
09 and 312. The D flip-flop 313°2 generator 314 operates similarly to a voltage controlled oscillator in a phase-locked circuit, and the sampling clock generator 302
The adder 312 operates so that the phase rotates 3606 times at a frequency that is 1/2 of the sampling frequency of the adder 312, that is, the same frequency as the channel data rate, and the phase is controlled by the input signal from the input terminal of the adder 312. The D flip-flops 303, 306, 307, and 313 are supplied with clocks from the sampling clock generator 302. The digital phase synchronization circuit configured in this manner transfers digital data from the A/D converter 301 to D flip-flops 303, 306°, 307, phase calculation circuit 308. The operations of the phase comparator and loop filter are combined by the coefficient unit 310 and the AND gate 311 into the adders 309, 312 . The D-flip flops 313 and 2 generators operate as a voltage controlled oscillator. Therefore, the delay time of the phase-locked loop is determined by the adder 309. Subtraction circuit 308, coefficient unit 310
．． ANDGATE 311. This is the sum of the delay times of the adder 312 and the D flip-flop 313, and the upper limit of the operating frequency of this phase-locked circuit is limited by the delay time of this phase-locked loop. For example, the coefficient of the coefficient unit 311 is set to 1/
2' (β is a positive integer), the delay time is made zero by shifting the digits, and even if the adder 309 and the 2 generator 314 are replaced with inversion of the upper digits to increase the speed, n
-8, the upper limit of operation frequency using current TTL ICs is about 30 MHz as a sampling frequency. In other words, the conventional digital phase synchronization circuit has a channel data rate of 15 Mbps at current TTL.
It has the disadvantage that it can only be used in magnetic recording and reproducing devices of the order of 1.5 or less.

Further, since the loop filter in the conventional digital phase synchronized circuit shown in FIG. 5 is only the coefficient multiplier 310, the loop gain is small, and therefore the steady phase error is large. In order to reduce the steady phase error, coefficient multiplier 3 is used.
There is a method to increase the gain in the low frequency region of the loop by inserting a leaf integrator etc. instead of 10, but this increases the complexity of the loop filter circuit and increases the delay time as a phase-locked loop. , which further reduces the operating frequency.

(Problems to be Solved by the Invention) As described above, the conventional digital phase synchronization circuit has the drawback that it can only be used in magnetic recording and reproducing devices with a low channel data rate.

Furthermore, in conventional digital phase-locked circuits, if the loop filter is simplified in an attempt to increase the operating frequency, the steady-state phase error increases; conversely, in an attempt to reduce the steady-state phase error, the loop gain in the low frequency region of the loop filter is increased. This has the drawback of requiring a complicated circuit and lowering the operating frequency.

The present invention has been made with these points in mind, and one of its purposes is to provide a digital phase synchronization circuit that can be used in a high bit rate magnetic recording/reproducing device.

Another object of the present invention is to provide a digital phase synchronization circuit that can reduce steady-state phase errors without lowering the operating frequency.

[Structure of the Invention] (Means for Solving the Problem) In order to solve the first problem, the present invention processes the average phase in a plurality of intervals from data of three or more sampling points in parallel. It is possible to increase the operating frequency by calculating the phase of the phase synchronization circuit every multiple samplings. To calculate the average phase in multiple intervals between sampling points, calculate the sum of the absolute values of the sampling data at both ends of the interval where the zero cross exists and the absolute value of one of the sampling data over multiple intervals, and then use these average values to calculate the average phase. Calculate by division.

In addition, in order to solve the second problem mentioned above, this invention
After correcting the phase input signal to the phase-locked loop by performing calculations such as leakage integration on the low-frequency component of the phase error outside the phase-locked loop to correct the steady-state phase error,
The signal is input to a phase-locked loop of a simple loop filter that has the highest operating frequency.

(Function) According to the first configuration described above, since the calculation of the average phase in multiple intervals does not have a feedback loop, addition can be performed by simple parallel processing and pipeline processing can be performed, making it possible to increase the speed. .

Additionally, since a phase-locked circuit originally averages the instantaneous phase of an input signal, by correcting the phase at each sampling point using the average phase at multiple intervals, the delay time of the phase-locked loop can be adjusted. It becomes possible to handle frequencies higher than the determined frequency. According to this invention, for example, by calculating the average phase of eight intervals,
The sampling frequency can be increased to about 200 MHz, which is a great advantage if applied to a magnetic recording/reproducing device.

Furthermore, according to the second configuration, by calculating the low frequency region component of the phase error outside the conventional phase-locked loop and correcting the input phase, the operating frequency of the phase-locked circuit is not reduced. It is possible to reduce the steady phase error.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram of a digital phase synchronization path according to the first invention of the present application, and FIG. 2 is a waveform diagram for explaining the operation of FIG. 1. In FIG. 1, the configuration is such that the average phase of the four sampling point intervals is calculated using the data of five adjacent sampling points, and the phase is corrected for each of the four sampling points. In FIG. 1, a reproduced signal R obtained by amplifying a signal read by a reproducing head in a magnetic recording/reproducing apparatus by a preamplifier and equalizing its waveform by an equalizing circuit is input to an input terminal 100, and the A/D
is supplied to converter 101. It is assumed that a clock signal having a frequency twice the channel data rate is applied from the sampling clock generator 102 to the sampling clock input of the A/D converter 101. Input terminal 10
The reproduced signal R added to 0 is converted into digital data s, s by the A/D converter 101 as shown in FIG.
,...s,,sj+1.・Sj+2'
12 It is converted into S S, ,... Each of these data is parallel data of M (M is a positive integer) bits, but is shown by a single line in FIG. 1 as in the conventional circuit. A/D converted digital data is serially
The parallel conversion circuit 103 converts the four adjacent pieces of data so that they are output in parallel. The serial/parallel conversion circuit 103 is controlled by a sampling clock signal from a sampling clock generator 102 and an I's clock signal obtained by dividing the frequency of the sampling clock signal into 174 by a frequency divider 104. The four parallel data are further input to D flip-flop 105 and delayed by four sampling periods.

Further, among the four parallel data of the serial/parallel conversion circuit 103, only the data that was the first sampling point when it was serial data is also applied to the phase calculation circuit 106 and the zero cross detection circuit 107. Also, D flip-flop 105
The four parallel data delayed by the above are also applied to the phase calculation circuit 106 and the zero cross detection circuit 107. The phase calculation circuit 106 inputs data S, , S, 2 1 Sj of 5 adjacent sampling points.
+ 3 +S, as shown in FIG. The average position F is obtained by averaging the phases of the sections whose existence is detected.

That is, when there are five sampling points as shown in FIG. 2, for example, odd-numbered sampling point data S
, , the average phase θ for S j + 2 ゛S, is 3 + 4 θ , -(θ , ′ + θ , ′ ) /
2J Here, assuming θ, ′Σθ,′, θ is approximated by the following equation 3.

In general, division in digital operations is more complicated than addition or multiplication, so calculating the approximate phase using equation (8) is faster than calculating the phase using equation (2) using a simpler circuit. I can do it. In addition, since the calculations of equations (2) and (3) can be performed by vibrating processing, it is possible to prevent a decrease in the calculation speed even if the number of inputs in the calculation increases. Of course, the phase calculation using equation (3) involves an error, but since the phase is originally calculated by approximating a straight line between two sampling points, the error is of the same magnitude as the linear approximation, so there is no problem. Therefore, the phase calculation circuit 106 receives the control signal from the zero cross detection circuit 107 and calculates the sum of the absolute values of the sampling data on both sides of the interval where the zero cross exists among the four intervals between the five sampling points. The absolute value of one sampling data is added or averaged over 4 intervals, and by dividing them, 4
Approximately calculate the average phase at sampling point intervals.

The output of the phase calculation circuit 106 is a D flip-flop 108.
Then, the output of the zero cross detection circuit 107 is applied to the shift register 10 via an OR circuit 109. The number of stages of the shift register 10 is selected so as to compensate for the time required for the phase calculation circuit 106 to process the vibe line. The output θ of the D flip-flop 10B is the subtraction circuit 111.
The output of the D flip-flop 112, θ, is subtracted, and the signal is further added to the coefficient multiplier 113, where it is multiplied by a coefficient K (where Q<K≦1). The output of the coefficient unit 113 is K
(θ, -θ). The output of the coefficient J O generator 113 is added to one input of an AND gate 114 and is connected to an OR circuit 109 via a shift register 10.
It is opened and closed by the output of The OR circuit 109 outputs "1 degree" when a zero cross is detected somewhere between the five sampling points by the zero cross detection circuit 107, and outputs "0 degree" if the zero cross is not completely heated. As a result, the AND gate 114 is controlled via the shift register 110, and the output of the AND gate 114 is set to O when there is no zero cross. The output of the AND gate 114 is the adder 11
5 and is the output of the D flip-flop 112.
is added and input to the D flip-flop 112. The output of the D flip-flop 112 is output to an output terminal 116 as an output of the phase locked circuit. The output of the period divider 104 is output from the D flip-flop 105°108.
112. Phase calculation circuit 106. In the digital phase synchronized circuit configured in this manner, which is supplied as a clock signal to the shift register 110, the subtraction circuits 111. Coefficient unit 113. The AND gate 114 serves as a phase comparator and a loop filter, and the adder 115 and the D flip-flop 1
12 operates as a voltage controlled oscillator. And A
After the digital data from the /D converter 101 is converted into parallel data by the serial/parallel conversion circuit 103, the f's clock signal of 1/4 of the sampling frequency is used to
Since the phase calculation and the D flip-flop etc. are operated, the circuit of FIG. 1 is replaced by the A/D converter 101. Sampling clock generator 102. Series/parallel conversion circuit 1032
By excluding the frequency divider 104 and using a TLL IC, the sampling frequency can be increased to about 120 MHz. In the ff11 diagram, phase synchronization is performed using the average phase of the four sampling point intervals, but
For example, if we decide to calculate the average phase at intervals of 8 sampling points, the sampling frequency will be approximately 240 MHz, and the channel bit rate will be 120 Mbit/sec.
It is possible to construct a digital phase synchronization circuit that can handle high-speed digital signals on the order of c.

Note that this invention is not limited to the above embodiments.

In the above embodiment, five sampling points were used to calculate the average phase, and the average phase at four intervals was calculated, but the average phase may be calculated using three or more sampling points. It may be selected depending on the channel data rate of the reproduced signal, the delay time of the IC used, etc. If the number of sampling points used to calculate the average phase is increased, a higher-speed digital phase synchronization circuit can be constructed, but the phase calculation becomes more complicated and the frequency range over which phase synchronization can be achieved becomes smaller.

The circuit shown in Figure 1 uses the simplest coefficient filter as a loop filter, but in order to reduce steady-state phase errors, etc., a more complex loop filter including an integrator or leakage integrator is used to improve the characteristics of the phase-locked circuit. Improved circuit configurations are also possible.

Next, an embodiment of the second invention of the present application will be described.

FIG. 3 is a block diagram of a digital phase synchronization circuit according to the present invention, and FIG. 4 is a detailed block diagram of a leakage integrator for explaining the operation of FIG. 3. In FIG. 3, an input terminal 200 receives a reproduced signal read out by a reproducing head in a magnetic recording/reproducing device, amplified by a preamplifier, and equalized in waveform by an equalization circuit.
is supplied to converter 201. It is assumed that a clock signal having a frequency twice the channel data rate is applied from the sampling clock generator 202 to the sampling clock input of the A/D converter 201. Input terminal 200
The reproduced signal added to is converted into digital data S1°S, . . . , Sl, Si+1' by the A/D converter 101.
It is converted to... These data are 'hb
Although it is parallel data of t (hx is a positive integer) bits, it is shown by a single line in FIG. 3 as in the conventional circuit. The digital data is applied to the D flip-flop 203, the phase calculation circuit 204, and the zero cross detection circuit 205, and the output delayed by one sampling period by the D flip-flop 203 is applied to the phase calculation circuit 204, the zero cross detection circuit 205, and It will be done. The phase calculation circuit 204 is the fifth
Similar to the phase calculation circuit 304 in the conventional digital phase synchronization circuit shown in the figure, this circuit calculates the phase expressed by equation (1) from input data S 1 and S 2 . Zero cross detection circuit 2
05 is also a circuit that detects the existence of a zero cross between adjacent sampling points, similar to the one in Figure 5.
The case where the signs of and S are different is detected. The outputs of the phase calculation circuit 204 and the zero loss detection circuit 205 are applied to D flip-flops 206 and 207, respectively.
Latched by sampling clock signal. The output of the D flip-flop 206 is connected to an adder 208 and a subtracter circuit 20.
Added to 9. The subtraction circuit 209 uses the output of the D flip-flop 206, θ1 of equation (1), to the adder 210.
is the output from which θ is subtracted, and is added to the other input of the adder 208 via a low-pass filter 211 composed of a wire integrator or the like. Adder 2
The output of 08 is latched by the D flip-flop 212, and the zero-cross detection signal of the zero-cross detection circuit 205, which is the output of the D flip-flop 207, is also latched by the D flip-flop 213 in order to adjust the delay time. The output of the D flip-flop 212 is the subtraction circuit 2.
14, the output of the adder 210 is subtracted, and the coefficient is added to the coefficient unit 215, where the coefficient K (however, Q<K
≦1). The output of the coefficient multiplier 215 is applied to one input of an AND gate 216, which is opened and closed by the zero cross detection signal that is the output of the D flip-flop 213. In other words, when a zero cross is detected, the coefficient unit 215
AND gate 21 so as to add the output of
6 is opened, and the output of the AND gate 216 is set to 0 when a zero cross is not detected. The adder 217 adds the output of the AND gate 216 and the output of the adder 210 and inputs the sum to the D flip-flop 218.
The output of is applied to adder 210. n of adder 210
-1n-1 Constant data of 2 is added from the 2 generator 219 to the other inputs. Further, the output of the D flip-flop 218 is output to an output terminal 220. Similar to the conventional digital phase synchronization circuit shown in FIG.
．． Coefficient unit 215. The AND gate 216 constitutes a phase comparator and a loop filter, and the adders 210 and 21?
, D flip-flop 2182 The generator 219 operates as a voltage controlled oscillator whose phase is controlled by the input signal to the adder 217. D flip-flop 203,
206, 207, 212, 213, 218 and low pass filter 211 are clocked by sampling clock generator 202.

FIG. 4 shows an example of the low-pass filter 211 in FIG. 3, which constitutes a leakage integration circuit. In FIG. 4, an input terminal 400 has the output of the subtraction circuit 209 in the third circuit, and an input terminal 401 has the output of the sampling clock generator 2 of FIG.
Receives clock supply from 02. A signal from an input terminal 400 is applied to an adder 402, added to the output of a subtraction circuit 403, and input to a D flip-flop 404. The output of the D flip-flop 404 is applied to a subtraction circuit 403 and a coefficient multiplier 405. 'The coefficient unit 405 multiplies the output of the D flip-flop 404 by a coefficient (k is a positive integer) by bit shifting the output of the D flip-flop 404. A leakage integration circuit is constructed by subtracting the output of . The output of the D flip-flop is connected to an output terminal 406 which provides an output to adder 208 in FIG.

In the digital phase synchronization circuit configured as described above, the low frequency region component of the phase error signal that causes the steady phase error is added to the adder 208. A subtractor 209 and a low-pass filter 211 form a subtraction circuit 214 . which is a conventional phase-locked loop. Coefficient unit 215, AND gate 216. Adder 210°217, D flip-flop 218.2
The calculation is performed outside the phase-locked loop consisting of the generator 219, and the input phase signal is corrected in advance to reduce the steady-state phase error. The high-frequency component of the phase error signal is operated by a phase-locked loop constituted by a coefficient multiplier 215, which is the simplest conventional loop filter, and does not degrade the operation of the phase-locked circuit. That is, the digital phase synchronization circuit of FIG. 3 according to the present invention can reduce the steady phase error without lowering the operating frequency.

Note that this invention is not limited to the above embodiments.

In the above embodiment, the phase is calculated from two sampling points, but by calculating the average phase from three or more sampling points, it is also possible to obtain a higher-speed digital phase synchronization circuit. In short, this invention can be implemented with various modifications without departing from its gist.

〔Effect of the invention〕

As explained above, the digital phase synchronized circuit shown in FIG. By correcting the phase of the phase-locked loop at each sampling point, it is possible to operate at a sampling frequency that is more than twice the frequency determined by the delay time of the phase-locked loop. Therefore, it will be of great advantage if used as a digital phase synchronization circuit in a high-speed magnetic recording/reproducing device for digital signals such as a digital VTR.

In addition, the digital type (color) U synchronized circuit shown in FIG. 3 according to the second invention calculates the low frequency component of the phase error that causes the steady phase error by leakage integration etc. outside the phase locked loop, and calculates this phase The low frequency component of the error reduces the operating frequency of the phase locked loop by inputting it into the phase locked circuit of a simple loop filter such that the operating frequency is the highest after correcting the phase input signal to the phase locked loop. Therefore, it is very advantageous to use it as a digital-type hue-matching g1 circuit in a high-speed digital signal magnetic recording/reproducing device such as a digital VTR.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of a digital phase synchronization circuit which is an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining Fig. 1, and Fig. 3 is an embodiment of the invention. A block diagram of a digital phase-locked circuit, FIG. 4 is a detailed block diagram of a leakage integrator to explain the operation of FIG. 3, FIG. 5 is a block diagram of a conventional digital phase-locked circuit, and FIG. 6 5 is a waveform diagram for explaining FIG. 5. FIG. 101.301...A/D converter 102.302...Sampling clock generator 10
3... Column parallel conversion circuit 105.108, 112, 303, 306°307.3
13...D flip-flop 106.304...Phase calculation circuit 107.305...Zero cross detection circuit 111.308
... Subtraction circuit 113, 310 ... Coefficient unit 115, 309, 312 ... Adder 201 ... A/D converter 202 ... Sampling clock generator 203, 2
06. 207. 212. 213°218.404
...D flip-flop 204...Phase calculation circuit 205...Zero cross detection circuit 209.214,403...Subtraction circuit 215.405
・・・Coefficient unit

Claims (3)

[Claims] (1) The reproduced waveform of the digital signal is sampled at a frequency equal to or higher than the channel bit rate, and based on the values of three or more adjacent sampling points, the digital signal at intervals of a plurality of adjacent sampling points intersects the reference level. 1. A digital phase synchronized circuit, characterized in that the phase synchronized circuit is configured to calculate an average phase from a certain sampling point to a predetermined sampling point, and to synchronize in phase with the calculated average phase. (2) Calculation of the average phase is based on the sum of the absolute values of the values of the sampling points on both sides of the sampling point interval where there is a point where the digital signal intersects the reference level among the plurality of adjacent sampling point intervals, and The digital phase synchronized circuit according to claim 1, wherein the absolute value of the value of the sampling point on the side of . (3) Sample the reproduced waveform of the digital signal at a frequency higher than the channel bit rate, and calculate the difference between the reference level of the reproduced waveform of the digital signal between the adjacent sampling points based on the values of two or more adjacent sampling points. A digital phase-locked circuit configured to calculate the phase or average phase from an intersection to a predetermined sampling point and synchronize with the calculated phase or average phase using a phase-locked loop, has a low phase error. A frequency domain component is calculated in advance outside the phase-locked loop, and the low-frequency domain component of the calculated phase error is used to correct and input the phase input signal indicating the calculated phase or average phase to the phase-locked loop. A digital phase synchronized circuit characterized by: