JPS63261430A - Information processing method and device - Google Patents

Abstract

PURPOSE:To speed up the execution speed of an information processor by managing a control device by a control managing device, removing the redundancy of a control instruction and reducing the load of execution processing. CONSTITUTION:An instruction developing device 2 reads out a machine instruction from a storage device 5 and develops the read instruction into a control instruction having a lower level. The control managing device 1 detects a case that an instruction is unrequired by executing a precedently developed control instruction, a case that an instruction precedently developed and not executed yet is unnecessary, or a case that a control instruction can be integratedly simplified out of the developed control instruction string. The device 1 informs the detected result to an instruction executing device 3 and the device 3 executes the control instruction. Since the devices 2, 1 operate simultaneously with the device 3, a part which can not be optimized before a compiler executes an objective table can be controlled so as to be optimized at the time of execution. Consequently, the execution speed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to information processing devices such as computers, and particularly to an execution optimization method suitable for large-scale numerical calculations.

[Conventional technology]

The conventional device is "Compiler" written by Ikuo Nakata, Sangyo Tosho (
As discussed in Chapter 10, ``Optimization of Objective Floors,'' published in 1981, the objective floor was analyzed in advance and an objective floor that was expected to improve execution efficiency was generated. . Alternatively, in non-optimizing compilers, the redundancy of runtime control was ignored.

[Problem that the invention seeks to solve]

The above conventional techniques can only be applied to the extent that the objective floor can be analyzed statically, so in cases where the execution order of the objective floor includes a part where the execution order is dynamically determined, static analysis is not possible, or the compiler Analysis is not performed across procedures with different processing positions. In other cases, it is impossible to perform a complete static analysis due to compiler processing time and available memory constraints, and optimization is not possible in such cases. There was a problem with points remaining.

The purpose of this invention is when the execution order of the objective floor is determined dynamically, when the compiler does not perform completely static optimization, or when the objective is created directly without using the compiler. , by eliminating control redundancy during execution of the destination floor.

, the purpose is to reduce the burden of execution processing.

[Means for solving problems]

The purpose of the control device is to function as an instruction expansion device that expands machine instructions into lower-level control instructions, and an instruction execution device that operates each part of an information processing device using the expanded control instructions.
This is achieved by providing a control management device that omit and integrate control commands that have been further divided into two parts.

[Effect]

The instruction expansion device reads machine instructions from the storage device and expands them into control instructions at a lower level than the machine instructions.6 The control management device reads out machine instructions from the storage device and expands them into control instructions that are at a lower level than the machine instructions. Detects and informs the instruction execution device when there are instructions, control instructions that have been expanded previously and have not yet been executed, are unnecessary, or those control instructions can be combined and simplified, and the instruction execution device makes changes. Execute an abbreviated or abbreviated control command after it has been specified.

Since the instruction expansion device and the control management device operate simultaneously with the instruction execution device, the compiler can perform optimized control at the time of execution even for portions of the target floor that cannot be optimized before execution.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Second
In the figure, 5 is a storage device in which data and machine instructions to be processed are stored. 8 is an instruction address register indicating an address on the storage device 5 where a machine instruction to be executed is located. Reference numeral 9 denotes an instruction data register into which a machine instruction placed at the address indicated by the instruction address register 8 on the storage device 5 is loaded. Reference numeral 11 denotes an instruction decoding device that decodes the data in the instruction data register 9 and sends the decoding result to the control instruction synthesis circuit 10. Reference numeral 7 denotes a register content management device, which determines the redundancy of machine instructions to be executed based on data matching information between registers and memory held in the register/memory equivalent information storage device 6, and determines the redundancy of machine instructions to be executed. It is detected that the control command is unnecessary, or a simpler control command is found and sent to the control command synthesis circuit 10. The control instruction synthesis circuit 10 synthesizes the information sent from the register content management device 7 and the instruction decoding device 11 and sends the control instruction to each part of the information processing device. A register 12 exchanges data with the storage device 5. What is the difference between the storage device 5 and the register 12?

Registers have a faster access speed and operations are performed on registers, but they have fewer numbers and a smaller storage capacity. The effect of this embodiment is that unnecessary data transfer between the register 12 and the storage device 5 is avoided by the register content management device 7, thereby reducing the processing load and increasing the processing speed accordingly.

The register/memory equivalent information storage device 6 contains register and memory matching information. That is, each register has information as to whether the register is equal to the data at a specific address on the memory or is undefined. It is initially set to be undefined at the start of execution. In order to represent this information, we use a 1-bit flag that is 0 if undefined and 1 otherwise, and an address value on memory (equivalent memory address value) with matching contents if undefined. Each register has a corresponding one.

The register content management device 7 refers to the register/memory equivalent information storage device 6 and informs the control instruction synthesis circuit 10 that the machine instruction to be executed is unnecessary or will be replaced with a simpler instruction.

However, if the address on the memory is an address assigned to an input/output device rather than a storage device, the instruction is not replaced.

An important point in this device is that the register content management device 7 operates simultaneously with the decoding of a machine instruction to instruct a change in the instruction. Therefore, unlike the storage device ff5, the register/memory equivalent information storage device 6 can be referenced and defined at high speed only by the register content management device 7.

Hereinafter, the register/memory equivalent information storage device 6 and the register content management device 7 will be explained in more detail with reference to FIG. In FIG. 3, 13 is a register equivalent storage comparison circuit, 14 is a register equivalent storage setting circuit, and 15 is a register content management device control circuit.

The control circuit 15 transfers the contents of the command data register 9 to the signal line 6.
6, and performs the following operations depending on the type of instruction. In the following explanation, R1°Rj represents an arbitrary register, and M represents an arbitrary memory address.

■ LoadRagister Ri t Rj Outputs a request to compare Ri and Rj to the signal line 74, and outputs a request to set the information of Ri to the information of Rj to the signal line 75.

■ Load Ri, M Outputs a request to compare Ri and M and a request to detect registers equivalent to M to the signal line 74, and outputs a request to set the information of Ri to M to the signal line 75.

5tore Ri, M A request to compare Ri and M is sent to the signal line 74, and a request to set M and equivalent register information to undefined is output to the signal line 75, and a request to set the information of Ri to M is output to the signal line 75.

■Memory M reference command Add Ri, M equidistant line 7
Send a request to M4 to detect registers equivalent to M.

■ Register Ri change command Add Ri, sends a request to the M equal confidence branch 75 to set the information of Ri to undefined.

■ (Excluding ■) Memory change command C1ear Issues a request to the M equivalence branch 75 to set M and equivalent register information to undefined.

The comparison circuit 13 receives a request from the control circuit 15 from the signal line 74, and performs the following operations in response to the request.

■ Comparison request for Ri and Rj Register/memory equivalent information About the information on Ri and Rj in the storage device 6 1 If both are not undefined (flag is 1) and the equivalent memory address values are equal, execute the command to the signal line 69 Outputs that it will be ignored.

■ Comparison request for Ri and M If the information on Ri in the register/memory equivalent information storage device 6 is not undefined (the flag is 1) and the equivalent memory address value is equal to M, the execution of the command to the signal line 69 is ignored. Outputs the fact that it is done.

0M and equivalent register detection request register/memory equivalent information storage device 6 that is not indefinite (
Flag 1) detects one register whose equivalent memory address value is equal to M, and if any, sends signal [69
outputs a message indicating that the reference to M is to be changed to that register.

When the comparison circuit 13 completes the above-mentioned requested processing, or if there is no request, it instructs the setting circuit 14 to permit operation through the signal line 72.

The setting circuit 14 performs the following operation in response to a request from the signal line 75 at the time when the setting circuit 14 is instructed to permit operation from the signal line 72.

■Set the information of Ri to the information of Rj If the information of Rj in the register/memory equivalent information storage device 6 is not indefinite (the flag is 1), copy the equivalent memory address value to the information of Ri and set the flag to 1. do. When the information on Rj is undefined (the flag is 0), the information on Ri is made undefined (the flag is 0).

(2) Setting the information of Ri to M For the information of Ri in the register/memory equivalent information storage device 6, set the equivalent memory address value to M and set the flag to 1.

(2) Set the information of Ri to be undefined Set the flag to O for the information of Ri in the register/memory equivalent information storage device 6.

A register that sets the information of registers equivalent to 0M to be undefined.
It is not undefined (the flag is 1) in the memory equivalent information storage device 6.
) Set the flag to 0 for all registers whose equivalent memory address value is M.

Figure 1.1 shows a flowchart of the processing method.

Next, the execution of the object shown in FIG. 4 will be explained as an example.

In FIG. 4, R1 and R2 are registers, S and A.

I, B are addresses on memory, 0.1 is a constant, LOI,
LO2 represents a label.

After executing the Load instruction in step 101, the information regarding R1 in the register/memory equivalent information storage device 6 is set to be undefined (the flag is O).

Before executing the 5tore instruction in step 102, the information regarding R1 in the register/memory equivalent information storage device 6 is undefined (
Since the flag is 0), execution of the 5tore instruction is not ignored. After the instruction is executed, the equivalent memory address value is determined by the information in the register/memory equivalent information storage device 6 before execution.
Undefined if there is a register set to (flag is O)
, and the equivalent memory address value of the information regarding R1 is set to S.

If the information regarding R2 in the register/memory equivalent information storage device 6 is not indefinite and the equivalent memory address value is set to A before executing the Load instruction in step 103, then L
If the oad instruction is not executed, or if the information in the register/memory equivalent information storage device 6 is not indefinite and there is a register whose equivalent memory address value is set to A, the L
The oad instruction is replaced with the LoadRegister instruction and executed.

After the instruction is executed, the register/memory equivalent information storage device f!
The equivalent memory address value of the information regarding R2 in 6 is set to A.

Before the execution of the 5jOre instruction in step 104, the equivalent memory address value of the information regarding R2 in the register/memory equivalent information storage device 6 is set to A, and since A and address are different addresses, the execution of the 5tore instruction is not ignored. After execution, if there is a register whose equivalent memory address value has been set to E before execution in the information in the register/memory equivalent information storage device 6, it will be set to undefined (flag is O), and information regarding R2 will be set to the equivalent memory address value. Address value is set to I.

Before executing the Load instruction in step 105, step 10
The Load instruction is not executed because the information regarding R1 in the register/memory equivalent information storage device 6 is not indefinite and the equivalent memory address value is set to S by executing the instruction 2.

After executing the Add instruction in step 106, the information regarding R1 in the register/memory equivalent information storage device 6 is set to be undefined.

Before executing the 5tore instruction in step 107, register/memory equivalent information storage l! Since the information regarding R1 in 6 is undefined, the execution of the 5tore instruction is not ignored.
After executing the instruction, register/memory equivalent information storage bag! !
! If there is a register whose equivalent memory address value is set to S before execution in the information in R1, it is set to undefined (flag is 0), and the information regarding R1 has its equivalent memory address value set to S.

Control moves to the Ca1l instruction actual instruction up subroutine in step 108. The state of the information in the Ca1l total 1l instruction actual register/memory equivalent information storage device 6 cannot be determined only from the objective sheet shown in FIG.

If the information regarding R2 in the register/memory equivalent information storage device 6 is not indeterminate and the equivalent memory address value is set to "E" before executing the Load instruction in step 109, the Lo
If the ad instruction is not executed, or if the information in the register/memory equivalent information storage device 6 is not indefinite and there is a register whose equivalent memory address value is set to
The ad instruction is replaced with the LoadRegister instruction and executed.

After the instruction is executed, the equivalent memory address value of the information regarding R2 in the register/memory equivalent information storage device 6 is set to ■. If the Ca1l instruction actual instruction upstream R2 in step 108 has not been changed, 5to in step 104
By executing the re instruction, the information regarding R2 in the register/memory equivalent information storage device 6 is changed to the equivalent memory address value I.
, the Load instruction is not executed.

After executing the Add instruction in step 110, the information regarding R2 in the register/memory equivalent information storage device 6 is set to be undefined.

Before the execution of the 5tore instruction in step 111, the information regarding R2 in the register/memory equivalent information storage device 6 is undefined, so the execution of the 5tors instruction is not ignored.
If there is a register whose equivalent memory address value is set to ``English'' before execution, it is set to undefined (the flag is O), and the information regarding R2 has the equivalent memory address value set to ``Engine''.

If the information in the register/memory equivalent information storage device 6 is not indefinite and there is a register whose equivalent memory address value is set to B before executing the Compare instruction in step 112, the Compare instruction returns CompareRegist.
It is replaced with the er instruction and executed.

If the value of R2 is less than or equal to the value of B by the Branch instruction in step -13, control is transferred to step 105 indicated by label LO1.

In the Load command of step 105 from the second time onwards.

R1 in the register/memory equivalent information storage device 6 before execution
If the information related to this is not undefined and the equivalent memory address value is set to S, the Load instruction will not be executed. That is, if the Ca1l instruction actual instruction upstream R1 and S in step 108 are not changed, the 5tor in step 107
By executing the e instruction, the equivalent memory address value of the information regarding R1 in the register/memory equivalent information storage device 6 is set to S, so the Load instruction is not executed.However, only from the objective sheet shown in FIG. This cannot be determined.

In this way, the loop is executed until the value of R2 is increased by 1 with A as the initial value until it becomes larger than B. However, since the values of I and B may be changed within the subroutine indicated by LO2, it is not determined how many times the loop will be repeated.

Even if an optimizing compiler or the like attempts to optimize the target score before execution, it is not possible to delete the Load instructions in steps 105 and 109 because the Ca1l instruction in step 108 exists.

Furthermore, even if there is no Ca1l command in step 108 or if the control within the subroutine indicated by label LO2 can be completely analyzed, there is a possibility that the values of S and K may be changed due to an interruption during execution of the target score. If there is, the Load command in steps 105 and 109 cannot be deleted.

Also, if the analysis results show that the Load instruction is always required from the second time onwards, but not the first time,
Although the Load command in step 105 cannot be omitted as the target score, according to this embodiment, the first Load command is ignored during execution.

According to this embodiment, analysis may not be possible before execution;
Even if the command can be analyzed but cannot be omitted on the target score due to control confluence, etc., the processing burden can be reduced by not executing unnecessary loads from memory to registers and stores from registers to memory during execution. can be reduced and executed at high speed.

In the above embodiment, the register/memory equivalent information storage device 1
Although the information in 6 has only one address value on memory that matches one register, it can be expanded to have two or more address values. In this way, the number of cases in which instructions can be simplified can be increased.

Figure 5 shows the register/memory equivalence information storage bag when one register is expanded to hold information on equivalence with the contents of two or more addresses on memory! F2
6 and a register content management device 7 in detail.

The portion corresponding to the register memory equivalent information storage device 6 is a register group storage device 21 and a memory group storage device 22. The parts corresponding to the register content management device 7 are a comparison circuit 23, an unused group detection circuit 24, a setting circuit 25, and a memory group registration area selection circuit 26.

27 control circuits.

Internal representations of register group storage 21 and memory group storage 22 are shown in FIGS. 6 and 7, respectively. A register group storage 21 indicates the group to which each register belongs, and a memory group storage 22
indicates the group to which the contents of a certain address in memory belong. The contents of registers and memories in the same group are equivalent.

The areas 21-1 to 21-m in FIG. 6 contain information on each group number for all m registers. The areas 22-1 to 22-k in FIG. 7 can store group numbers for up to a maximum of memories. In each of the GN areas, a group number is stored, and an address value on the memory is stored in MA. The group number is an integer value from O to m. O indicates that it does not belong to any group, that is, the equivalence with memory or other registers is undefined, and other values indicate the same group number. Indicates that the values in the registers and memories held are equivalent.

The comparison circuit 23 compares the contents of the register group storage device 21 and the memory group storage device 22 under the control of the control circuit 27, and if the instruction is ignored or changed, it is sent to the control instruction synthesis circuit 10 through the signal line 69. Outputs the message. In addition, the unused group detection circuit 2 is connected to the signal line 86.
4 of the operation timing, and informs the setting circuit 25 of the comparison result through the signal line 89.

For m integers from 1 to m, the unused group detection circuit 24 detects m-1 areas from areas 21-1 to 21-m excluding the area 21-1 corresponding to the designated register Ri. Detects a group number (other than 0) that is not used in any register other than the specified register in the register group storage device 21 by comparing it with the group number of any area and determining that it does not match the group number of any area. Then, one of them is sent to the setting circuit 25 through the signal line 87, and all the unused group numbers mentioned above are sent to the memory group registration area selection circuit 26 through the signal line 79.

The setting circuit 25 determines the operation based on the control of the control circuit 27 and the comparison result of the comparison circuit 23 received through the signal line 89, and selects the unused group number specified from the unused group detection circuit 24 or the memory group registration. Information on the memory group registration area specified by the area selection circuit 26 is used as necessary to set the contents of the register group storage device 21 and the memory group storage device 22.

The memory group registration area selection circuit 26 selects an area in the memory group storage device 22 in which a new memory and group number correspondence is to be registered.

If there is a region whose GN is O, that region is selected. If there is no GN with O, and if there is an ON belonging to the unused group number notified from the unused group detection circuit 24 through the signal line 79, that area is selected. In other cases, the information is transmitted to the memory group registration area selection circuit 26 through the signal line 85 each time the memory group storage bag M22 is referenced or set, and the information is transmitted to the memory group registration area selection circuit 26 every time the memory group storage bag M22 is referenced or set. It has relative time order information, and the information of the oldest referenced and set area is discarded as the new area to be registered.

The control circuit 27 transfers the contents of the command data register 9 to the signal line 6.
The comparator circuit 23 and the setting circuit 25 are controlled so that each section in the register content management device 7 performs the following operations depending on the type of instruction.

■ Load Ragister Ri, Rj comparison circuit 23 has Rj group number not O.

If it is equal to the group number of Ri, a message indicating that the command is to be ignored is output to the signal line 69.

If the group number of Rj is not O and the group number of Ri is not equal to this, the setting circuit 25 sets the group number of Ri to the group number of Rj.

If the group number of Rj is O, the unused group detection circuit 24 detects a group number g that is not used in any register other than Ri in the register group storage device 21.
(other than O), and if the setting circuit 25 finds one in the memory group storage device 22 where GN is equal to g, O
Ri of the register group storage device 21
and set the group number of Rj to g.

■ Load Ri, M The memory address value is M in the memory group storage device 22, and the group number is not O but a register.
If the group number is equal to the group number of Ri in the group storage device 21, the comparison circuit 23 outputs to the signal line 69 a message indicating that the command is ignored.

In the memory group storage table W122, the memory address value is M, and its group number is not O, but R of the register group storage device 21 (a register different from Ri).
If it is equal to the group number of j, the comparison circuit 23 sends a command to the signal g69.
, Rj, and the setting circuit 25 sets the group number of Ri to the group number of Rj.

In cases other than the above, the unused group detection circuit 24 finds an unused group number g (other than O) in the registers other than Ri in the register group storage device 21, and the setting circuit 25 searches the memory group storage table. ff!
22, if there is one whose GN is equal to g, it is rewritten to 0, the group number of Ri in the register group storage table r121 is set to g, and the memory group selected by the memory group registration area selection circuit 26 is The setting circuit 25 registers the group number g in the GN and the memory address value M in the MA of the area in the memory bag e22.

■ 5tore Ri, M memory group memory table! ! ! 22, if the memory address value is M and its group number is not O but equal to the group number of Ri in the register/group storage device 21, the comparison circuit 23 sends a number to the signal line 69 indicating that the command is to be ignored. Output.

Otherwise, if the group number g of Ri is not 0, if there is an area with the memory address value M in the memory group storage table @22, set the group number to O for all of them, and Selection circuit 26
G of the area in the memory group storage device 22 selected by
The setting circuit 25 registers the group number g in N and the memory address value M in MA.

If the group number of Ri is 0, then the memory group storage! 22 and the memory address value is M.
If there is an area, set the group number to O for all of them, and then use the unused group detection circuit 24 to find a group number g (other than 0) that is not used in any register other than Ri in the register/group storage device 21. , the setting circuit 25 is a memory group storage device! If there is something in 22 where GN is equal to g, change it to 0.

The group number of Ri in the register/group storage table [21 is set to g, and the memory group registration area selection circuit 26
Selected memory group storage device! A setting circuit 25 registers a group number g in GN and a memory address value M in MA in the area within 22.

■Memory M reference instruction Add Ri, M, etc. The memory address value is M in the memory group storage device 22, and its group number is not 0 but has the same group number in the register group storage device 21. If there is a register Rj, the comparison circuit 23 outputs to the signal line 69 a message indicating that the memory M reference instruction is to be changed to the register Rj reference instruction.

(2) Command to change register Ri Add Ri, M, etc. setting circuit 25 sets the group number of Ri in register group storage device 21 to O.

■ (Excluding ■) Memory M change order pc1ear M etc. memory group storage device! At step 222, if there is an area whose memory address value is M, the group number is set to 0 for all of them.

FIG. 12 shows a flowchart of the processing method.

The following will explain the execution of the objective score shown in FIG. 8 as an example.

In FIG. 8, R1 is a register, A.

Represents an address on B memory.

In the first implementation □ example, the equivalence of R1 and A is defined after the execution of the instruction in step 121, but since only one address in memory can be stored for one register, the instruction in step 122 is executed. When the equivalence between R1 and B is defined later, the information on the equivalence between R1 and A is lost, and there is a problem in that the instruction in step 123 is executed even though it is redundant. In this embodiment, the instruction in step 123 is not executed because the information on the equivalence of R1 and A and the equivalence of R1 and B remain.

As a result, the instructions can be simplified in more cases than in the first embodiment, and can be executed faster.

In this embodiment, if a group number other than O in the register group storage device 21 or memory group storage device 22 is not valid, that is, if the group number of a register in the register group storage device 21 is different from that of another register. This is necessary if there is no same group number in the memory or memory, or if the group number used in the memory group storage device ff22 is a group number that is not used in the register group storage device 21. It is said that the group number will be reset or made undefined at this point.
A method may also be adopted in which the point in time when a group number becomes invalid is detected and the group number is immediately made undefined.

As another embodiment, as shown in FIG. 9, a control instruction buffer 29 may be provided to store the decoding results of a plurality of instructions, and a control instruction simplification device 28 may change the control contents before execution. Conceivable.

The control command simplification device 28 reads the control commands stored in the control command buffer 29, and simplifies the control commands in the control command buffer 29 if possible.

The control command buffer 29 is a command decoding device! 11, the control instruction string resulting from decoding the machine instructions is received and processed as a first-in, first-out (FIFO) buffer, and the first control instruction is transferred to the signal line 70 by an external control execution signal.
Output from.

This makes it possible to perform more simplified control depending on the combination of instructions that are executed several instructions earlier. Furthermore, although optimization cannot be achieved at the level of the objective score, that is, the command word, control may be simplified depending on the combination of commands at the control command level when one command word is expanded to multiple control commands. .

The following will explain the execution of the target score shown in FIG. 10 as an example. In Figure 10, R1 is a register, 0°1 is a constant, and N
is an address on the memory, and R03゜LO4, LO5 are labels.

After O is loaded into R1 with the Load instruction in step 131, 1 is added to R1 with the Add instruction in step 132. These two instructions can be replaced with the same control as the instruction that loads 1 into R1 during execution. Step 13
Since control from other sources merges into 2, it is not possible to replace the command on the destination score.

Also, after the Ca1l instruction in step 135, step 13
Since there are 6 branch instructions, Ca1l total 1l instruction actual bell L
Address when returning from subroutine indicated by O5,
That is, in the control of saving the address of the instruction in step 136 to a stack or the like, #Jll can be simplified by setting this address to be saved as the address of the instruction in step 132 indicated by label LO3. This optimization cannot be done at the target score level.

〔Effect of the invention〕

According to the present invention, since the control device can be managed by the control management device and the redundancy of control instructions can be reduced,
This has the effect of increasing the execution speed of the information processing device. This is done when executing the target score obtained without using a compiler with an optimization function, or for parts that cannot be analyzed by a compiler with an optimization function or parts that cannot be optimized with a machine instruction level target score. It is also possible to perform optimized control by using information in the control management device during execution. In addition, compared to a method in which the objective score is expanded to the level of control instructions before execution, the method of the present invention stores it at the level of machine instructions, so the memory size can be reduced to a fraction of that. . In particular, when the same part is executed many times due to repetition, etc., it may be impossible to expand to the control instruction level due to storage capacity constraints, but with the method of the present invention, expansion is performed at the time of execution. It is possible to implement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus of the present invention, FIGS. 2 and 3 are block diagrams of an embodiment of the present invention, and FIG. 4 is an example of a goal score, which is an embodiment of the present invention. FIG. 5 is a block diagram of another embodiment of the present invention. FIG. 6 is an explanatory diagram showing the internal representation of the register group storage device of the present invention. FIG. 7 is a block diagram of another embodiment of the present invention. FIG. 8 is an explanatory diagram showing the internal representation of the storage device, FIG. 8 is an example of a target score, and is an explanatory diagram of another embodiment of the present invention. FIG. 9 is a block diagram of another embodiment of the present invention. FIGS. 11 and 12, which are examples of objective scores and are explanatory diagrams of other embodiments of the present invention, are flowcharts showing the processing method of the present invention. 1... Control management device, 2... Command expansion device, 3...
- Instruction execution device, 5... Storage device, 6... Register memory equivalent information storage device, 7... Register content management device. 8... Instruction address register, 9... Instruction data register, 10... Control instruction synthesis circuit, 11... Instruction decoding device, 12... Register, 13... Register equivalent storage comparison circuit, 14 . . . Register equivalent memory setting circuit, 15 . . . Register content management device control circuit, 21 .
・Register, ・Group storage device, 22...Memory
Group storage device, 23... Comparison circuit, 24... Unused group detection circuit, 25... Setting circuit, 26...
-Memory group registration area selection circuit, 27...control circuit. 28... Control instruction simplification device, 29... Control instruction buffer, 51-54% 62-75. 79-94... Signal line, 101-113, 121-123, 131 3
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-/θ7Call LD2
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d Rr, A ”'123 Lotd R1,0-131 Lθ3: Add R1,l...13
2CompLlre R1,/V =, 133Bra
nch, Bin LO4-134Call LO
5...135 BranCh L03 = 136 yen; rt1j
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Claims (1)

[Scope of Claims] 1. An information processing method, characterized in that the information processing method includes a step of managing control commands. 2. The information processing system according to claim 1, wherein equivalence between a register and a memory is stored in the management step. 3. The information processing system according to claim 2, wherein the equivalence with one memory is stored for each register. 4. The information processing system according to claim 2, wherein the equivalence is stored as a group number between registers or memories. 5. The information processing system according to claim 1, wherein a buffer is provided in the management step to store control commands resulting from decoding machine commands, and the control commands are changed before execution. 6. An information processing device, characterized in that the information processing device includes a control management device that manages control commands. 7. The information processing device according to claim 6, wherein a storage device is provided in the control management device to store equivalence between a register and a memory. 8. The information processing apparatus according to claim 7, further comprising a storage device for storing the equivalence with one memory for each register. 9. The information processing apparatus according to claim 7, further comprising a storage device that stores the equivalence using a group number between registers or memories. 10. The information processing device according to claim 6, wherein the control management device is provided with a buffer for storing control commands resulting from decoding machine commands, and the control commands are changed before execution. . 11. An information processing method characterized in that a control step is divided into an instruction expansion step and an instruction execution step and executed in parallel. 12. An information processing device characterized in that the control device is divided into an instruction expansion device and an instruction execution device and executed in parallel.