JPS63260212A - Pulse noise reduction circuit - Google Patents

Abstract

PURPOSE:To obtain a pulse noise reduction circuit having a large ratio in digital IC adoption by providing a trigger circuit section including a prescribed sample hold circuit in place or a high-order active high-pass filter. CONSTITUTION:When an input voltage Vc is inputted to each input terminal of a transmission circuit section 1 and a trigger circuit section 2 in a pulse noise reduction circuit, a sample hold circuit 6 samples an input voltage Vi including a noise pulse P at a period of, e.g., 5mus and holds the sampling voltage Vs till the next period. Thus, the leading of a first pulse P1 included in the voltage Vs is retarded by a time tau. Then voltages Vi and Vs are subtracted in a differential amplifier A2 and a waveform including a pulse P2 having a pulse width tau1 with the same leading as the pulse P is obtained as the output. Then the rectified output Vr is obtained through a full wave rectifier circuit 7 in response to both bipolar properties of the pulse P. Denoting the reference voltage of the comparator circuit 8 as Es, then the trigger pulse Vt synchronously with the pulse P2 is obtained and an output voltage V0 is obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a pulse noise reduction circuit.

[Conventional technology]

With the recent spread of high-quality radios, there is a demand for audio equipment that allows users to enjoy high-quality music even in noisy environments.

For example, in an FM radio as an electrical component of a car, pulse noise of about 5 to 50 μs from inside and outside the car is likely to mix into the audio circuit.

Conventional pulse noise reduction circuits extract only the pulse noise component from an audio input signal that contains pulse noise, and block signal transmission for a certain period of time using a transmission gate circuit installed in the signal transmission circuit to eliminate the pulse noise. had been removed.

FIGS. 3(a) and 3(b) are a block diagram of an example of a conventional pulse noise reduction circuit and a circuit diagram of a high-pass filter.

As shown in FIG. 3(a), the pulse noise reduction circuit has a reduction filter 3 inputting the input voltage V+, an integral signal V of the reduction filter 3 inputted to the input terminal, and a control terminal connected to a single signal with a pulse width τ0 μS. A transmission circuit section 1 includes a transmission gate circuit 4 inputting the output of a stable multivibrator 5, a holding circuit consisting of a capacitor C, and an amplifier A1 connected in series, a high-pass filter 13 receiving an input voltage V at its input terminal, and a high-pass filter 13 receiving an input voltage V from the output terminal. The trigger circuit section 12 includes a waveform shaping circuit 14 that supplies a trigger voltage Vt to the monostable multivibrator 5.

As shown in FIG. 3(b), the high-pass filter 13 is a feedback type active filter consisting of capacitors C1 to C6, resistors R1 to R6, and amplifier A4, and has a cut-off frequency of approximately 6 dB at 100 kHz, which is sufficiently higher than the audio frequency. /10kHz maintains steep filter characteristics.

The low-pass filter 3 corresponds to the high-pass filter 13 and has a CR element and an amplifier, and has the same cut-off frequency of 100 kH.
It consists of z active filters.

FIGS. 4(a) to 4(e) are voltage waveform diagrams of various parts for explaining the operation of the circuit of FIG. 3.

As shown in FIG. 4(a), 100 to 2
An input voltage (1) in which pulse noise P with a width of 5 to 100 μs is superimposed on a 0 kHz audio waveform is input.

As shown in FIG. 4(b), the input signal V+ is about 5 to 1
In order to eliminate the time τ2 of about 0 μs, the low-pass filter 3 of the transmission circuit section 1 is applied with an integrated voltage ■l containing pulse noise P4.
is obtained and input to the transmission gate circuit 4.

As shown in FIG. 4(c), since the input signal VI simultaneously passes through the high-pass filter 13 of the trigger circuit section 1, a differential voltage Vh of the pulse noise component is obtained.

This differential voltage Vh passes through the waveform shaping circuit 14, has its polarity and pulse width adjusted, and becomes a trigger voltage (2) for triggering the monostable multivibrator 5.

As shown in FIG. 4(d), the pulse gate voltage ■G of the monostable multivibrator 5 has a pulse width τ0 of 10 to
It is set to 50 μs.

As shown in FIG. 4(e), the input gate voltage V turns the integrated voltage VJ at the input end into an off state for a time τ0.

The signal holding capacitor C is for holding the voltage level of the immediately preceding waveform during the period τ0 in which the transmission gate circuit 4 is in the off state.

Therefore, the output voltage Vo has a waveform with reduced pulse noise P.

Note that the low-pass filter 3 is related to the requirements for the cutoff characteristics of the high-pass filter 12, and if a high-order high-pass filter is used to make the characteristics ideal, the rise time of the pulse noise P,
Since the rise points of the off-state of the transmission gate circuit 4 coincide with each other, it is unnecessary or can be simplified, but in this case, the differential voltage Vh becomes weak and a high-performance waveform shaping circuit is required instead.

[Problem that the invention aims to solve]

The conventional pulse noise reduction circuit described above uses a high-pass filter with steep cutoff characteristics in order to sharply separate the input signal and pulse noise components, so in order to faithfully improve pulse noise reduction performance, it is necessary to There is a problem in that the number of CR elements in the high-pass filter increases, and the precision of the constants of these elements is also required.

Also, if the time constant of the filter circuit is designed to exceed 5 μs, the value of the capacitor used will exceed 1009F, so the IC
There was also the problem that it could not be converted into

An object of the present invention is to provide a pulse noise reduction circuit with a large digital IC ratio.

[Means for solving problems]

The pulse noise reduction circuit of the present invention includes: (A) a low-pass filter whose input terminal receives an input voltage;
a transmission gate circuit whose input end inputs the integrated voltage of the low-pass filter, whose control end inputs the output pulse of the monostable multivibrator as a gate voltage, and which does not allow the integrated voltage to pass during the period of the output pulse. (B) a sampling hold circuit whose input terminal receives the input voltage, samples the input voltage at a predetermined period, holds the voltage until the next sampling time, and outputs a step-like sampling voltage; a differential amplifier circuit whose input terminal inputs the input voltage and the sampling voltage and whose output terminal outputs the difference voltage; and a full-wave rectifier circuit whose input terminal inputs the differential voltage and whose output terminal outputs the rectified voltage. and a comparator circuit whose two input terminals input the rectified voltage and the reference voltage and whose output terminal supplies the trigger voltage to the input terminal of the monostable multivibrator.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a block diagram and a circuit diagram of a sampling and holding circuit according to an embodiment of the present invention.

The transfer circuit section 1 is the same as that shown in FIG. 3, except for the trigger circuit section 12, which includes the differential amplifier A2 of the sampling and hold circuit 6, the full-wave rectifier circuit 7, and the comparator circuit 8.

As shown in FIG. 1(a), the output terminal of the input terminal T1 of the low-pass filter 3 is connected to the input terminal of the transmission gate circuit 4. As shown in FIG.

The output terminal of the transmission gate circuit 4 is connected to a signal holding capacitor C whose one end is grounded, and is also connected to the input terminal of an amplifier A, and the output terminal of the amplifier Al is connected to an output terminal To of the transmission circuit section 1. be done.

In addition, the input terminal T1 is connected to the input terminal of the sampling and holding circuit 6 and also to one input terminal of the differential amplifier A2, and the output terminal of the sampling and holding circuit 6 is connected to the other input terminal of the differential amplifier A2. be done.

The output terminal of the differential amplifier A3 passes through a full-wave rectifier circuit 7, and is connected to a comparator circuit 8 to which a reference voltage ES is applied to one input terminal.
The output terminal of the comparison circuit 8 is connected to the input terminal of the monostable multivibrator 5.

The output end of the monostable multivibrator is the transmission gate circuit 4
is connected to the control end of the

As shown in FIG. 1(b), the sampling hold circuit 6 includes a sampling circuit S, a differential amplifier A3, and a feedback resistor R.
s, a capacitance Jt Cs, and a grounding resistance RE.

The sampling circuit S inputs the input voltage ■1 to the differential amplifier A3.
When inputted to the negative input terminal of the oscillator for several microseconds at a periodic interval of 5 to 10 microseconds, for example, through a transmission gate circuit of a MOS FET, a step-like sampling voltage Vs is obtained which holds the previous sample value during the off-state period.

Here, the resistor RS has a value of 10 to 20 Ω, and the capacitor C5 has a value of about 10 to 100 PF, so these are constants that can be integrated into an IC.

2(a) to 2(e) are signal waveform diagrams of various parts for explaining the operation of the circuit of FIG. 1.

As shown in Fig. 2(a), the input voltage ■1 is applied to the transmission circuit 1.
and are input to the respective input terminals of the trigger circuit 2, but the operation of the transmission circuit section 1 is the same as the conventional one.

As shown in FIG. 2(b), the sampling and holding circuit 6 samples the input signal 1 containing the pulse noise P at a period of 5 μs, for example, and holds the sampling value VS until the next period, so the sampling The rise of the first noise pulse P1 included in voltage ■5 is input signal ■
1 and the rise of the nozzle pulse P by τ1 time.

As shown in FIG. 2(C), in the differential amplifier A2, the input signal Vl is subtracted by the step-like sampling voltage VS, so its output is a combination of the total sampling value and the current input signal VI. As the output of the difference, a waveform including a pulse P2 having the same rise as the noise pulse P and a pulse width τ5 is obtained.

Furthermore, in order to cope with both the positive and negative polarities of the noise pulse P, a rectified output voltage (1) is obtained through a full-wave rectifier circuit 7.

Here, when the reference voltage of the comparator circuit 8 is set to Es, a trigger pulse V synchronized with the noise pulse P2 is obtained.

As shown in FIGS. 2(d) and (e), the same waveform as in FIGS. 4(d) and (e) is obtained as the output voltage Vo.

That is, the characteristics of the transmission circuit section 1 are the same as the conventional one.

In this embodiment, the low-pass filter 3 is the same as the conventional one, but in the present invention, the rise time t1 of the gate voltage Va is exactly the same as the rise time 1 of the pulse noise P of the input voltage. The required time constant is 10, which is the conventional value.
It can be reduced to ~50%, the circuit configuration is simple, and the element constants of resistors and capacitors can be made small enough to be integrated into ICs.

〔Effect of the invention〕

As explained above, the present invention has the effect that a pulse noise reduction circuit with a large digital IC ratio can be obtained by providing a trigger circuit section including a sampling and holding circuit in place of the conventional high-order active high-pass filter. There is.

[Brief explanation of drawings]

1(a) and 1(b) are a block diagram and a circuit diagram of a sampling and holding circuit of an embodiment of the present invention, and FIG. 2(a) is a block diagram of an embodiment of the present invention.
) to (e) are voltage waveform diagrams of various parts to explain the operation of the circuit in Figure 1, Figures 3 (a) and (b) are conventional circuit diagrams, and Figures 4 (a) to (e). 3 is a voltage waveform diagram of each part for explaining the operation of the circuit of FIG. 3. FIG. 1... Transmission circuit section, 2... Trigger circuit section, 3...
Low-pass filter, 4... Transfer gate circuit, 5... Monostable multivibrator, 6... Sampling hold circuit, 7... Full wave rectifier circuit, 8... Comparison circuit, A1
...Amplifier, A2, A3...Differential amplifier,
Es...Reference voltage, V+...Input voltage, VG...
Gate voltage, v, r...low-pass filter output voltage, ■o
...output voltage, ■, ...rectified output voltage, Vs...
Sampling voltage, Vt...Trigger voltage.

Claims (1)

[Claims] (A) A low-pass filter whose input terminal receives an input voltage, whose input terminal inputs the integrated voltage of the low-pass filter, and whose control terminal inputs the output pulse of a monostable multivibrator as a gate voltage. (B) an input terminal receives the input voltage and samples the input voltage at a predetermined period until the next sampling time; a sampling hold circuit that holds the voltage and outputs a step-like sampling voltage; and a differential amplifier circuit that has two input terminals that input the input voltage and the sampling voltage, and an output terminal that outputs the difference voltage between them. a full-wave rectifier circuit whose input terminal inputs the differential voltage and whose output terminal outputs the rectified voltage;
a trigger circuit having two input terminals for inputting the rectified voltage and a reference voltage and an output terminal for supplying a trigger voltage to the input terminal of the monostable multivibrator. .