JPS63258072A - field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a field effect transistor, and in particular to a field effect transistor, a gate electrode, a gate insulating film provided in contact with the gate electrode, and a field effect transistor provided in contact with the gate insulating film. The present invention relates to a staggered structure field effect transistor having a semiconductor layer, and a source electrode and a drain electrode that are ohmically connected to the semiconductor layer and provided on both sides of a gate electrode.

[Conventional technology]

A conventional field effect transistor of this type is shown in FIG.

203 (hereinafter referred to as 1-a
-8id) and the source 'C [located between the electrode 202 and the drain electrode 201] on the opposite side with the doped amorphous silicon layer 208 in between. Gate electrode 2
When a positive voltage is applied to 05, 1-a-8i/J
Electrons are accumulated at the interface between 203 and the gate insulating layer 204, and 1
-a-8i layer 20BKn-type channel is generated, and when a negative voltage is applied, holes are accumulated at the interface between 1-a-8i layer 203 and gate insulating In 2 (14) to generate a p-type channel. Source electrode 202 and drain electrode 2
01 could be made conductive.

FIG. 4 schematically explains the operation when a positive voltage is applied to the gate f (f-pole) using a band diagram.

FIG. 4 tal shows the gate electrode 405 and gate insulating layer 404°1 when no voltage is applied to the gate electrode 405.
An energy band diagram of the -a-8A layer 403 is shown.

In the (7) state, the conduction band (F,
In c), there are almost no carriers 409, and there is no conduction between the source 202 and drain electrode 201. When a positive voltage (Vg>O) is applied to the gate electrode 405, FIG.
), the band curves downward, and electrons 409, which become carriers, pass through the gate insulating layer 404 and the 1-a-8A layer 403.
, a channel is formed through which current flows, and conduction occurs between the drain 201 and the source electrode 202.

[Problem that the invention seeks to solve]

The above-mentioned conventional field effect transistor has 1-a by accumulating electrons or holes in the 1-a-8A layer.
An n-type or p-type channel is formed in the -8A layer. However, non-doped amorphous silicon does not originally have a high carrier density, and therefore has the disadvantage that the current flowing through the channel (hereinafter referred to as channel current) cannot be very large.

[Failure to solve the problem]

The field effect transistor of the present invention includes a gate electrode, a gate insulating layer provided in contact with the gate electrode, and a second gate electrode.
ohmic connection with the semiconductor layer and the second semiconductor layer,
It has a source electrode and a drain electrode provided at a predetermined distance apart from each other with the gate electrode in the center.

[Effect]

Between the gate insulating layer and the 1-a-8A layer (n"-a-8
1 or p''-a-84 has a high density of electrons and holes, which are carriers, so by placing it between the gate insulating film where the channel is formed and the 1-a-8A layer, the carriers can be reduced. The problem of not being able to obtain a large channel current due to increased density can be solved.

〔Example〕

FIG. 1 is a longitudinal sectional view of a first embodiment of the invention. In this embodiment, first, 80 OA of chromium is deposited on the glass substrate 106 by sputtering, and the gate electrode 105 is patterned. Next, a gate insulating layer 104 is formed, and amorphous silicon (n
"-a-:di) Active layer 107 20A, 1
-a-8A layer 1033000A.

An n+7a-8A layer tos 500X is sequentially formed, and chromium 2000A is again sputtered thereon.

After that, the uppermost chromium is selectively etched by dry etching to pattern the drain electrode 101 and the source electrode 102, and finally, the total -a-8A layer 108 is dug by dry etching to create a field effect. A transistor was formed.

Next, the operation of the present invention in this embodiment will be explained using a band diagram shown in FIG. Figure 3 (al is the gate electrode 3 when no voltage is applied to the gate electrode (Vg=0)
05. Gate insulating layer 304. n”-a-8A layer 307
, i-a-8A layer 303 schematically shows a band diagram. In this example, n+-a-8 with high carrier density
Since the A layer 307 exists, the gate insulating film 304 and 1-a-
The Ec-4 zone (Ec) between 8i 194303 is already close to the Fermi level. However, between the drain electrode and the source electrode, the Ec of i-a-81IVJ303 is far from the Fermi level and there are few carriers, so the conductivity is 11! !
It does not become a state. Here, a positive voltage (
When Vg>o) is applied, the band bends as shown in b) to form an n-type channel, and conduction occurs between the drain and source electrodes, but the carrier density and channel width of the channel at this time are both larger than before. , the current between the drain and source electrodes also increases.

FIG. 5 shows a voltage VD applied to the drain electrode 101 at IOV and a current l flowing between the source electrode and the drain electrode measured as a voltage Vge parameter applied to the gate electrode 105.
5-D characteristics are shown for the present invention and the prior art. The 15-D-Vg characteristic of the present invention clearly increases ISD compared to the conventional one.

As a second embodiment of the present invention, total-a-8i1 in FIG.
There is a version in which 07 and 108 are replaced with one using p-type doped amorphous silicon (p"-a-8i) k doped with boron. In this example, the carriers are holes, and the voltage applied to the gate electrode 105 There is an advantage that Vg can be set to a negative voltage.

〔Effect of the invention〕

As explained above, the present invention is realized by providing an n+-a-8i active layer or a p''-a-8i active layer with high carrier density between the 1-a-8i layer and the gate insulating layer depending on the channel. This has the effect of increasing the channel current with the same gate bias voltage compared to the conventional method.

Moreover, as a side effect, the n''-a-Si layer or p+
- Since there is a high-resistance 1-a-8i layer (■) between the -a-8i layer and the source and drain electrodes, the current level in the off state when no voltage is applied to the gate electrode is There is an effect that fx<fx is lower than that of a known device having only a doped amorphous silicon active layer as an active layer.

[Brief explanation of drawings]

FIG. 1 is a schematic longitudinal sectional view showing the structure of a field effect transistor according to an embodiment of the present invention, FIG. 2 is a schematic longitudinal sectional view showing the structure of a conventional field effect transistor, and FIG.
tbl is a band schematic diagram for explaining the operation of the field effect transistor of the first embodiment of the present invention, FIG.
t, (b) is a schematic band diagram for explaining the operation of a conventional field effect transistor, and FIG. 5 is a diagram showing the characteristics of the field effect transistor of the present invention. If) 1,20+...Drain electrode, 102
, 202... Source electrode, 103, 203, 3
03,403...-1-a-8i layer, 104,204
, 304, 404--...gate insulating layer, 105.
205.305.405...Gate electrode, 10
6,206...Substrate, 107°307--11
"-a -8i active layer, 108, 208-...-n
”-Ohmic contact layer using a-8i, 109...
...Electron. Agent Patent Attorney Susumu Uchihara 10f Nidoshi In 1 Branch Nese/θ2: N Z Electric A Shimo 1 Figure 2 7. ! ? : 71”-4-5i@m*Ij
: Ohmi, 7y”) 1夛1と/νTogi 2I! f Business 3N (a-) (b) Fig. 4

Claims (1)

[Claims] a gate electrode, a gate insulating layer provided in contact with the gate electrode, a first semiconductor layer provided in contact with the gate insulating layer and containing an impurity, and a first semiconductor layer provided in contact with the first semiconductor layer. , an electric field having a second semiconductor layer that does not contain impurities, and a source electrode and a drain electrode that are ohmically connected to the second semiconductor layer and are provided with a predetermined distance apart from the gate electrode. effect transistor.