JPS63255899A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the reliability of a parallel function test by providing a control signal line adjacently between plural data lines provided approximately in parallel. CONSTITUTION:A data bus 20 is composed of plural data lines 20-1-20-4, respective data lines 20-1-20-4 are extended approximately in parallel mutually adjoining along the edge of plural memory cell blocks 1-1-1-4 and further, all parts or a part of control signal lines 22-1-22-7 are provided adjacently between respective data lines 20-1-20-4. Here, when the data lines 20-1-20-4 and the control signal lines 22-1-22-7 are shorted by a metal remainder, etc., the signal on the data lines 20-1-20-4 and the signal on the control signal lines 22-1-22-7 mutually give an influence, and thus, the logical value of respective data lines is not mutually made coincident when plural bits having the same logical value are simultaneously read. Thus, the erroneous decision is prevented and the reliability in a parallel function test is improved.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor memory device having a memory cell group and reading and writing data to the memory cell group;
In particular, the present invention relates to a semiconductor memory device having a parallel function test function for simultaneously reading a plurality of bits of data from a memory cell array and determining the quality of memory cells in the memory cell array.

(Prior Art) Readable and writable semiconductor memory devices include static random access memory (hereinafter referred to as static RAM), dynamic random access memory (hereinafter referred to as dynamic RAM), and the like. Such a semiconductor memory device includes a memory cell group having a large number of memory cells, a decoder that decodes an address signal and selects a memory cell, a data bus connected to the memory cell group and having a plurality of data lines, and this data bus. It is comprised of an input/output circuit connected to the memory cell group for inputting and outputting data to and from the memory cell group, and a plurality of control signal lines for transmitting control signals for controlling the entire device.

In this type of semiconductor memory device, when performing a functional test to determine the quality of memory cells, a decoder sequentially selects each memory cell in a group of memory cells one bit at a time.
Each bit of stored data is sequentially output through a data bus and an input/output circuit to determine the quality of each memory cell.

However, in such a functional test, the test time becomes extremely long as the capacity of the memory cell group increases. Therefore, various proposals have been made to shorten the test time.

Conventionally, this type of semiconductor memory device has been described in, for example, Japanese Patent Laid-Open No. 61-59700.

In this semiconductor memory device, a detection circuit whose operation is controlled by a control signal is connected to a data bus, and the same data is written in each memory cell in advance for a functional test, and multiple bits are simultaneously read out by the detection circuit. The quality of each memory cell is determined by detecting whether the logical values of the data are all the same. By performing such a parallel functional test, it is possible to significantly shorten the test time.

(Problems to be Solved by the Invention) However, the semiconductor memory device having the above configuration has the following problems.

As the capacity of a memory cell group increases, the power consumption to drive them increases, so in order to reduce power consumption, the memory cell group is divided into multiple memory cell blocks, and each memory block is A split drive system is used that randomly selects and operates. Furthermore, as the capacity of the memory cell group increases, the chip size also increases, but in order to mount them in a case of a certain size, the chip size must be made smaller. As one method for adopting the split drive method and reducing the chip size, proposals have been made to further reduce the wiring area, particularly the overhead for forming a data bus having many data lines. In this method, a large number of data lines constituting a data bus are arranged substantially parallel to each other along the edges of a plurality of memory cell blocks, thereby reducing the wiring area.

However, as memory cell sizes gradually increase in capacity from 256 bits to 18 bits to 4H bits, it is not only necessary to narrow the pitch between each data line, but also as the number of memory cell blocks increases. The bus wiring length also increases. For example, in megabit class semiconductor memory devices, data buses are now wired to a length of about 10 mm with the minimum width and spacing allowed in wafer processing.

As the length of the data bus increases in this way, the statistical probability of metal residue occurring between each data line made of metal increases, and the probability that adjacent data will short-circuit to each other increases.

When each data line is short-circuited due to the presence of metal residue, the short-circuited data lines have the same logical value.

Then, as in the above-mentioned document, a parallel function test is carried out on a wafer or case of a device that is equipped with a detection circuit that determines normal function when the logical values of the data bus match, and determines abnormal function when there is a mismatch. In,
There is a problem in that an abnormal function is incorrectly determined as a normal function.

The present invention addresses the problems of the above-mentioned prior art, in order to suppress the increase in power consumption and increase in chip size due to the increase in memory capacity, the pitch between each data line becomes narrower and the data bus The object of the present invention is to provide a semiconductor memory device that solves the problem that the length increases, which causes short circuits between data lines and reduces the reliability of parallel functional tests.

<Means for Solving the Problems> In order to solve the above-mentioned problems, the present invention provides a memory cell group having a plurality of memory cells for storing data, and a memory cell group connected to this memory cell group and arranged almost in parallel. detecting a coincidence state of logical values of a data bus having a plurality of data lines connected to the data bus and a plurality of data simultaneously read from the memory cells through the data bus during a functional test of the memory cells; In a semiconductor memory device comprising a detection circuit and a plurality of control signal lines for transmitting control signals for controlling data writing and reading with respect to the memory cell group, there is a signal between the plurality of data lines. The control signal line is arranged adjacent to the data line.

(Function) According to the present invention, since the semiconductor memory device is configured as described above, by arranging the control signal line between each data line, the data line and the control signal line are short-circuited due to metal residue or the like. In this case, the signals on the data line and the signal on the control signal line influence each other, so that when reading multiple bits with the same logical value at the same time, the logical value of each data line will be the same as each other. I won't be able to do it. Therefore, a detection circuit that determines normal function based on the coincidence of the logical values determines that the function is abnormal. This prevents erroneous determinations and improves reliability in parallel functional tests. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a block diagram of a semiconductor memory device showing an embodiment of the present invention.

This semiconductor memory device is a readable/writable memory device using a memory cell group division drive method, and includes a plurality of divided memory cell blocks 1-1 to 1-4, and each of the memory cell blocks 1-1 to 1-4. Data bus 20 connected to 4
and a control signal generation circuit 21 which inputs the clock signal φ and the write/read signal Si and generates various control signals 81 to S7 for controlling the operation of this memory device. On the output side, a control signal 81
~Multiple control signal lines 22-1 for transmitting S7~
22-7 is connected. The data bus 20 consists of a plurality of data lines 20-1 to 20-4, and each of the data lines 20-1 to 20-4 connects a plurality of memory cell blocks 1-
Control signal lines 22-1 to 22-4 are provided adjacent to each other along the ends of the data lines 20-1 to 20-4 and extend substantially parallel to each other. All or part of 7 is provided.

Each memory cell block 1-1 to 1-4 is provided with a memory cell array 10 in which a large number of memory cells for storing data are arranged in a matrix. and a plurality of preamplifiers 13-1 to 13-4 are connected, and each of the preamplifiers 13-1 to 13-4 is connected to a plurality of main amplifiers 14.
-1 to 14-4, and read/write control circuit 15-1 to
15-4 is connected. The row decoder 11 is a circuit that decodes a plurality of address signals AD to select a row memory cell in the memory cell array 10, and the column decoder 12 decodes a plurality of address signals AD to select a column memory cell in the memory cell array 10. This is a circuit that does this. Preamplifier 13-
1 to 13-4 are main amplifiers 14-1 to 14, which respectively amplify the read data of a plurality of selected memory cells.
-5 is a circuit that amplifies the read data amplified by the preamplifiers 13-1 to 13-4 until the high level is near the power supply potential and the low level is near the ground potential. Further, the read/write control circuits 15-1 to 15-4, based on the control signal S1,
When reading data, the outputs of the main amplifiers 14-1 to 14-5 are output to the data bus 20 side, and when writing data, the signals on the data bus 20 are sent to the main amplifiers 14-1 to 14-5 and the preamplifiers 13-1 to 13-1. This circuit transmits data to the memory cell array 10 side through 13-4.

Furthermore, this semiconductor memory device is provided with an address buffer 23 for inputting a plurality of address signals AD at predetermined timing based on the control signal S2, and the output side of the address buffer 23 is connected to each memory cell block 1-1.
It is connected to the row decoder 11 and the column decoder 12 in . data bus 2
0 is connected to the input side of a detection circuit 26, and the output side of the detection circuit 26 and the output side of the multiplexer 25 are connected to an output circuit 28 via a control circuit 27. Further, the input side of the multiplexer 25 is connected to an input circuit 29 .

Here, the block decoder 24 is the address buffer 23
This circuit selects one of the plurality of memory cell blocks 1-1 to 1-4 by decoding 0 into the address signal from the memory cell block 1-1 to 1-4. The multiplexer 25 selects one of the plurality of data lines 20-1 to 20-4 constituting the data bus 20 based on the address signal AD from the address buffer 23, and transmits the selected 1-bit data. It also has a function of supplying the output of the input circuit 29 to the data lines 20-1 to 20-4 based on the control signal S3. The detection circuit 26 receives a control signal S4
Based on this, multiple data lines 20-
This is a circuit that detects whether all logical values of 1 match or not and provides the detection result to the control circuit 27, and is composed of an AND gate or the like.

The control circuit 27 is a circuit that provides the output of the multiplexer 25 to the output circuit 28 during a normal data read operation, and provides the output of the detection circuit 26 to the output circuit 28 during a parallel function test, based on the control signal S5. The output circuit 28 is a circuit that outputs the output data Do of the control circuit 27 at a predetermined timing based on the control signal S6, and the input circuit 29 outputs the input data Di at a predetermined timing based on the control signal S7.
This circuit inputs the signal and supplies it to the multiplexer 25.

FIG. 2 is a sectional view taken along line A--A in FIG. 1. In FIG. 2, data lines 20-1 to 20-4 are disposed on a semiconductor substrate 30 with an insulating film 31 interposed therebetween, and a control signal line 22-2 is provided between each data line 20-1 to 20-4. 5-22-7
is installed.

The operation of the semiconductor memory device configured as described above will be explained.

In a normal data write operation, input data Di is input to the input circuit 29 by the control signal S7 output from the control signal generation circuit 21, and transmitted onto the data bus 20 through the multiplexer 25. A plurality of supplied address signals AD are sent to the address buffer 2 by a control signal S2.
3, the input address signal AD is decoded by the block decoder 24, and one of the plurality of memory cell blocks 1-1 to 1-4, for example 1-1, is selected. In the selected memory cell block 1-1, the row decoder 11 and column decoder 12 decode the input address signal AD to select a memory cell to be written in the memory cell array 10. Then, the write/read control circuit 1
5-1 to 15-4 take in the input data O1 on the address bus 20 in response to the control signal S1, and input the input data D.
i is the main amplifier 14-1 to 14-4 and the preamplifier 13-
1 to 13-4 to write into the selected memory cell.

In a normal data read operation, for example, when reading data in the memory cell array 10 in the memory cell block 1-1, the data stored in the memory cell selected by the row decoder 11 and the column decoder 12 is transferred to the preamplifier 13-1.
1 to 13-4 and main amplifiers 14-1 to 14-4, and transmitted onto the data bus 20 through write/read control circuits 15-1 to 15-4. Then, multiplexer 25 selects 1-bit data on data bus 20 based on input address signal AD, and outputs it through control circuit 27 and output circuit 28 in the form of output data DO.

In such write and read operations, the block decoder 24 selects a plurality of memory cell blocks 1-1.
~1-4 are selected one by one. Therefore, compared to the power consumption of the selected memory cell block in the operating state, the power consumption of the unselected memory cell block in the standby state is sufficiently small, so that the power consumption of the entire device can be reduced.

Next, the operation of the parallel functional test on the memory cell array 10 will be explained.

For example, when testing the memory cell array 10 in the memory cell block 1-1 selected by the block decoder 24, the same 4-bit manual data Di corresponding to the number of data lines 20-1 to 20-4 is input to the input circuit. 2
9 and is transmitted onto the data bus 20 through the multiplexer 25. Then, memory cell block 1-1
In the write/read control circuits 15-1 to 15-4,
The 4-bit input data Di on the data bus 20 is taken in simultaneously, and the main amplifiers 14-1 to 14-4 and the preamplifier 1
3-1 to 13-4, 4-bit memory cells selected by row decoder 11 and column decoder 12 are simultaneously written. In this way, the same data is written into all memory cells in the memory cell array 10 in groups of 4 bits.

Thereafter, the row decoder 11 and column decoder 12 select four memory cells in the memory cell array 10, and transfer the 4-bit data to the preamplifiers 13-1 to 13-4 and the main amplifiers 12-1 to 14-4. and simultaneously supplies it to the data bus 20 through read/write control circuits 15-1 to 15-4. Then, the detection circuit 26 operated by the control signal S4 detects whether or not the logical values of the 4-bit data on the data bus 20 match, and outputs a corresponding detection signal through the control circuit 27 and the output circuit 28. . Therefore, based on the output of the output circuit 28, it is possible to determine a normal function if the logical values of the 4-bit data match, and to determine an abnormal function if they do not match. In this manner, each four bits are read out from the memory cell array 10 to determine the function. If the logical values of the 4-bit data do not match, the memory cell with the abnormal function can be found by performing a normal read operation and reading out the 4-bit data bit by bit.

By performing a parallel functional test of 4 bits as described above, the test time can be shortened.

Here, it is assumed that any of the data lines 20-1 to 20-4 and the control signal lines 22-5 to 22-7 are short-circuited due to metal residue or the like.

In general, the logic values of the control signals 81 to S7 and the time at which the logic values are generated are determined by the functions of the device, while the logic values of the data bus 20 change depending on the random logic value data that enters the device. Therefore, the control signal lines 22-5 to 22- are arranged adjacent to each other and substantially parallel to each other.
7 and the data lines 20-1 to 20-4 and a short circuit occurs, these control signal lines 22-5 to 22-2
2-7 and data lines 20-1 to 20-4 influence each other, and the control signal 85 is controlled by the logic value on the data bus 20.
~The logical value of S7 and the time at which the logical value occurs change, and normal function is inhibited.

Similarly, the logic values on data bus 20 correspond to control signals 85 to S.
It changes depending on the logical value of 7 and the time at which that logical value occurs. Therefore, when reading multiple bits having the same logical value at the same time, the logical values of the data lines 20-1 to 20-4 do not match each other, and therefore, the detection is determined to be normal function based on the matching of the logical values. The circuit 26 is determined to have an abnormal function. This makes it possible to prevent erroneous judgments that occur in conventional devices, and improves the reliability of parallel functional tests. Further, a control signal uA22 between each data line 20-1 to 20-4 is
Since -5 to 22-7 are arranged, an increase in the area of the wiring region can be prevented.

Note that the present invention is not limited to the illustrated embodiment; for example, the number of write and read bits during a parallel function test may be set to a number other than 4 bits, or the number of control signals 81 to $7 may be set to another number. Furthermore, it is also possible to modify the overall configuration of the semiconductor memory device into other configurations. Further, the present invention can be applied to other semiconductor memory devices in which memory cell groups are not divided and driven.

(Effects of the Invention) As described in detail above, according to the present invention, since the control signal line is arranged between and adjacent to a plurality of data lines arranged approximately in parallel, the wiring This can be expected to have the effect of improving the reliability of parallel functional tests without increasing the area of the area.

[Brief explanation of the drawing]

FIG. 1 is a structural block diagram of a semiconductor memory device showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line A--A in FIG. 1. 1-1 to 1-4... Memory cell block, 10
...Memory cell array, 11... Row decoder, 12... Column decoder, 15-1 to 15
-4...read/write control circuit, 20...
...Data bus, 20-1 to 20-4...Data line, 21...Control signal generation circuit, 22-1 to
22-7... Control signal line, 24... Block decoder, 25... Multiplexer, 2
6...Detection circuit, 27...Control circuit,
28...Output circuit, 29...Input circuit, AD...Address signal, Dl...Input data, Do...Output data, S1-S7・
·····Control signal.

Claims (1)

[Claims] A memory cell group having a plurality of memory cells that store data, a data bus having a plurality of data lines connected to the memory cell group and arranged substantially in parallel, and the data bus. a detection circuit connected to the memory cell for detecting a matching state of logical values of a plurality of data simultaneously read from the memory cell through the data bus during a functional test of the memory cell; and controlling writing and reading of data to and from the memory cell group. A semiconductor memory device comprising a plurality of control signals for transmitting control signals for transmitting control signals, characterized in that the control signal line is arranged between the plurality of data lines adjacent to the data lines. semiconductor memory device.