JPS63249976A - Clock extracting circuit - Google Patents

Abstract

PURPOSE:To stably eliminate a need of adjustment by adding a frequency comparator which generates the output in accordance with the frequency difference between the reference signal and a clock. CONSTITUTION:An input digital signal passes a gate 1 and has the phase compared with that of the clock by a phase comparator 2 unless it is not dropped out, and the clock has the frequency compared with that of the reference signal by a frequency comparator 7. Respective outputs are inputted to a loop filter after being added by an adder 3, and the output is inputted as the control voltage to a VCO 5, and the oscillation output has the frequency divided by 1/2 in a frequency divider 6 to generate the clock synchronized with the digital signal. If the digital signal is dropped out, the digital signal is stopped by the gate 1 and the output of the phase comparator 2 disappears, and therefore, the clock frequency is approximately equalized to the reference frequency by the frequency control of the frequency comparator 7. Thus, adjustment is unnecessary and the capture range is stable even in case of the variation of temperature, and slip of the clock for drop-out is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock extraction circuit for extracting a clock component contained in a digital signal to generate a reproduction clock in a digital signal reproduction apparatus.

2. Description of the Related Art In recent years, devices that reproduce digital signals, such as compact discs, digital audio tapes, and digital communications, have come into widespread use. These devices do not have a special reproduction clock, but generate the reproduction clock from a digital signal.

Conventionally, a phase-locked loop (hereinafter abbreviated as PLL) has been used as a clock extraction circuit for generating a reproduction clock.

FIG. 6 is a block diagram of a conventional clock extraction circuit.
2 is a phase comparator, 4 is a loop filter, 5 is a voltage controlled oscillator (hereinafter abbreviated as vC○), and 6 is a frequency divider.

The operation of the clock extraction circuit configured as described above will be described below.

First, the input digital signal is phase-compared with the clock in the phase comparator 2, and its output is input into the loop filter 4 having frequency characteristics as shown in FIG. It becomes the incoming clock, and the 6th
PL with response frequency characteristics as shown in figure (b)
A clock whose phase is synchronized with the digital signal is generated.

Problems to be Solved by the Invention However, in the conventional configuration described above, it is necessary to adjust the clock frequency of the digital signal to be at the center of the capture 0 range of the PLL, and the free-running frequency of the VCO may change due to temperature changes, etc. If the clock shifts, the capture range also shifts, causing problems such as the PLL not locking or the clock slipping with respect to the digital signal when the digital signal drops out.

The present invention solves the above-mentioned problems, and provides a clock extraction circuit that does not require adjustment, has a stable capture range even when there is a temperature change, and has less clock slips even in the event of a dropout.

Means for Solving the Problems In order to solve the above problems, the present invention adds a frequency comparator that generates an output according to the frequency difference between the reference signal and the clock, so that the free running frequency of the VCO is determined. In addition, a gate is used to stop the digital signal from being input in the event of a dropout.

Function: In the present invention, since the free-running frequency of the VCO is determined by the above-mentioned means, the clock frequency will be approximately at the center of the capture range even without adjustment, and the capture range will not change even if the element values change due to temperature changes, etc. few.

Furthermore, at the time of dropout, the VCO oscillates at a free-running frequency determined by the reference signal, which reduces clock slips.

Embodiment FIG. 1 is a block diagram of an embodiment of the clock extraction circuit of the present invention. In Figure 1, 1 is a gate, 2 is a phase comparator, 3 is an adder, 4 is a loop filter, 5 is a VCO, 6
is a frequency divider, and 7 is a frequency comparator 5\゛.

The operation of the clock extraction circuit of this embodiment configured as described above will be described below.

First, when the input digital signal is not dropped out, it passes through gate 1 and is phase-compared with a clock in phase comparator 2. Further, the frequency of the clock is compared with a reference signal by a frequency comparator 7. And each output is added to adder 3
and is input to a loop filter having frequency characteristics as shown in Fig. 2(a), its output is input to the VCO 5 as a control voltage, and its oscillation output has a response frequency that is divided by a frequency divider. A PLL is configured to generate a clock synchronized with a digital signal.

The reason why the gain curve curves at fc in FIG. 2(b) is because the clock frequency is controlled to approach the reference frequency by the function of the frequency comparator 7, so that the gain decreases in the control band.

In addition, when the digital signal drops out, the gate 61 -
.

1, the output of the phase comparator 2 disappears, and the clock frequency becomes almost the same as the reference frequency due to frequency control by the frequency comparator 7.

FIG. 3 is a specific circuit diagram of one embodiment of the clock extraction circuit of the present invention, and FIG. 4 is a timing chart thereof.

In Fig. 3, 11 (dOR gate, 12, 13°2
7. 32, 33, 34, 38, 39 are D flip-flops, 14. 15 UEX-OR game), 16, 17, 38
゜39 is a switch, 18, 19, 20, 21.22.4
2 is a resistor, 23.24 is a capacitor, 25 is an operational amplifier, 26ii: VCO, 28 is a counter, 29, 30
゜31.35 is a NAND gate, 36.37 is an AND gate, and in Fig. 4, a-j are timing charts corresponding to a-j in Fig. 3, and a-f and q-j are time axes. The scale of is different.

The operation of the clock extraction circuit of this embodiment configured as described above will be described below.

The trenchless OR gate 11 stops the digital signal when there is a dropout, and allows it to pass when there is no dropout.

5. A phase comparator is constituted by 7' and D-y flip-flops 12 and 13 and EX-OR14 and 15. The digital signal a passed through the OR gate 11 becomes D at the rising edge of the clock.
It is latched by the flip-flop 12 and becomes C, and further latched by the D flip-flop at the falling edge and becomes d. A and C become e by EX-OR14, and C and d become f by EX-OR15. The pulse width of e is wide when the clock is too fast, and narrow when the clock is too slow. f
The switch 16 is turned on by f, and the switch 17 is turned on high, and when it is too slow, it becomes low. Also, operational amplifier 25 and R20
, 21, 22, C23, and 24 constitute a loop filter, and R42, which will be described later, also serves as an adder to which the output of the frequency comparator is added.

R18 and R19 provide a bias voltage to the operational amplifier 25. The output of the operational amplifier 25 controls the oscillation frequency of the VCO 26, and in the case of a connoct disc player, the oscillation frequency normally operates around 8.6436 notes. The output of the VCo 26 is frequency-divided by a D flip-flop 27 into a clock b which operates around a normal frequency of 4.3218 hK with a duty of -50. This clock b is a clock extracted from the digital signal, and the D flip-flop 12 becomes a data signal shaped in the time axis direction by the clock b. Counter 28, NAND gate 29° 30.31, 35, AND gate 36.37
, D flip-flops 32 , 33 , 34 , 38
, 39 constitute a frequency comparator, and the frequency is 88.2kHz.
The reference signal z is frequency-divided by the D flip-flop 32 to create a reference signal with a duty of -50%, which is converted into a signal q synchronized with the clock b by the D flip-flop 33, and a trigger pulse is generated by the D flip-flop 34 and the NAND gate 35. is generated, the RS flip-flop formed by NAND gates 30 and 31 is inverted, and the h signal becomes H, and the counter 2
Start 8. When the counter 28 counts 49 clocks, the NAND gate 29 outputs the NAND gate 30.
and 31 to 9 - The RS flip-flop is inverted and becomes the h signal (dL. When the clock frequency is just right, q and h overlap, but when it is too fast, the H section of Fih becomes short and the AND gate 36 When it is too slow, the H section becomes long and a pulse signal j is generated from the AND gate 37.I and j are processed by D flip-flops 38 and 39 to remove the hazard caused by the difference in gate delay, and the switches 40 and 4
1 is activated and added to the operational amplifier 25 via the resistor 42.

In the eleventh embodiment, a phase control loop filter and a frequency control loop filter are commonly used, but they may be separated, and although the adder and the loop filter are configured with a common operational amplifier, they may be configured separately.

Effect of the invention As described above, according to the present invention, vc.

Even without adjusting the free-running frequency of the VCO, the free-running frequency of the VCO tends to approach the reference frequency of 8.6436+, so the clock frequency becomes approximately in the center of the cap challenge range, reducing temperature characteristics and element variations. Since it is hardly affected by 0 l -, it can be stably made unadjusted.

Furthermore, at the time of dropout, the VCO oscillates at approximately the reference frequency, so there is little clock slip, which has the effect of being resistant to dropouts.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clock extraction circuit in Embodiment 1 of the present invention, FIG. 2(a) is a frequency characteristic diagram of its loop filter, and FIG. 2(b) is a response frequency characteristic diagram of the entire loop. FIG. 3 is a specific circuit diagram of a clock extraction circuit that can be used in one embodiment of the present invention, FIG. 4 is a timing chart thereof, and FIG. 6 is a block diagram of a conventional clock extraction circuit. 6(a) is a frequency characteristic diagram of the loop filter, and FIG. 6(b) is a response frequency characteristic diagram of the entire loop. 1...Gate, 2...Phase comparator, 3
... Adder, 4 ... Loop filter,
5... VCo, 6... Frequency divider, 7...
...Frequency comparator. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure Groff's phase 1--Udera. , Speed 1 - insert. Special opening UG3-24997G (5) Fig. 5 Fig. 6'Y■) U2 ,)1\, -Surrounding...11\ -゛'''-

Claims (2)

[Claims] (1) A phase comparator that generates an output according to the phase difference between the digital signal and the clock, a frequency comparator that generates an output according to the frequency difference between the reference signal and the clock, and the output of the phase comparator and the frequency A clock extraction circuit comprising a loop filter that adds the outputs of a comparator to give necessary frequency characteristics, and a voltage-controlled oscillator whose oscillation frequency changes according to a control voltage. (2) The clock extraction circuit according to claim 1, further comprising a gate that blocks the digital signal by a dropout signal.