JPS6324764A - Exposure control circuit for ccd solid-state image pick-up element - Google Patents

Abstract

PURPOSE:To eliminate the need for another power source to set an accumulating electric potential by transferring an accumulating charge during a horizontal blanking period in the reverse direction, changing a reverse transmitting timing and obtaining an optimum exposure,condition, at a photodetecting area in a photodetecting condition. CONSTITUTION:A video signal derived from a video processing circuit 12 is inputted through an integrating circuit 12, a sampling circuit 14, and a low pass filter 15 to an AD converting circuit 16 and a reverse transferring pulse generating circuit 17 derives a reverse transferring pulse. For the reverse transferring pulse generating timing, when AD converting data are larger, the generating timing is delayed and when they are smaller, the timing is quickened. A changing-over pulse generating circuit 18 outputs the AND output of the reverse transferring pulse and a horizontal blanking pulse as a changing-over pulse, and a clock selecting circuit 19 selects and derives the reverse transferring clock. The accumulating charge transferred from a photodetecting area 1 to an accumulating area 2 comes to be the charge accumulated after the reverse transferring and the generating timing of the reverse transferring pulse controls an exposure.

Description

DETAILED DESCRIPTION OF THE INVENTION "(a) End of industrial application field" relates to an exposure control circuit for a CCD solid-state image sensor.

(b) Conventional technology Exposure braking in television cameras usually uses an iris control circuit to control the aperture mechanism inside the lens barrel, which increases costs.
Issued on the day! Revision Society Journal @ Volume 33 #! , No. 7 No. 5
On pages 36 to 541, in order to switch the photoelectric conversion speed during the light reception period into two stages, the storage electrode is set to the first electric potential, which is lower than the conventional 'g1 charge transfer transmission voltage, and the second electric potential, which is lower than the first electric message.
The exposure control circuit is configured to obtain a constant imaging output level A/ by selectively applying +1 (+t) and changing the switching timing of both potentials according to the imaging output level. ing.

Hereinafter, the specific groove bottom of the above-mentioned prior art will be explained in detail. First, Figure 2 shows a frame transfer type COD
This is a diagram for explaining the disturbance of a solid-state imaging device, and the device has a light receiving area +
It consists of a B and Jf control area (2), a horizontal successive register (3), and a preamplifier (4), and both areas each have 4-phase vertical feed locks (DAL) to (-4 and (-SL)). ~
(g s4) is applied to the horizontal register (4), and the two-phase horizontal 1 red clock (〆Hl) (aH2) (3, 5
8MH2) is applied.

The vertical transmission lock applied to the light receiving area (1) is the vertical transmission lock (Da 1) (Da 2) of the first and second phases applied to the first and second electrodes, and the vertical transmission lock (Da 1) (Da 2) applied to the fJ3 and fourth electrodes. Vertical transmission locks (g68) (da4) of the third and fourth phases are applied, respectively. 1st to 3rd i in the maku light receiving area! ! At the very bottom is the n-channel, -! N10 channels are formed under the 9th and 4th electrodes, and when the K1 and 2* poles reach a high level/l' during the light accumulation period (during the light reception period), the potential state of the light reception area changes. The state is as shown in FIG. 3, and the photoelectrically converted charges are accumulated under the second electrode.

FIG. 4 shows the output waveforms of each vertical transmission lock. As is clear from the figure, in the prior art described above, the first phase and second phase vertical transfer lock (DA1) (
When data 2) becomes a high repeat and charges are accumulated, the second potential (CVo) is lower than the first potential (CVo) which is the transfer potential.
By setting Vk) and changing the switching timing of both potentials, the optimum exposure state of the image sensor is fully realized. That is, during the optical accumulation J91 (the second potential application period tk at 0
As the time becomes longer, the accumulated charge is limited, and on the other hand, as the time becomes shorter, it tends to increase. Accumulate 8 like this! The stored charges controlled by the quantity j are transmitted over the storage area +21K times during the charge transmission period within the vertical blanking period.

During this forward transfer period, the duty cycle is set to 50
% vertical transfer lock is issued in the order of 1st phase (11), 2nd phase (da 2), 3rd phase (da 8), and 4th phase (da 4), and the accumulated charge is transferred in the forward direction. and transfer it to all accumulated charge advance payment accumulation areas (2).

The transferred accumulated charges are vertical transfer lock (dasl)~(
54) According to K, the horizontal blanking period length is transferred to the horizontal register (3) at a rate of one line per horizontal period. The S product charge transmitted to the horizontal register (3) is derived during the video signal period in synchronization with the horizontal transfer lock (LTL) (OH2), and is derived as an imaging output after the preamplifier (4) is fully operated.

(c) Problems to be Solved by the Invention However, in the case of the above-mentioned conventional example, a separate power source is required to set a potential different from the R transfer potential as the storage potential. do not have.

(d) Means for Solving the Problems Therefore, the present invention provides a frame transfer type CCD solid-state image sensor in which charges accumulated in the light-receiving area are directed in the opposite direction to the accumulation area during the horizontal blanking period. A reverse transfer means for transmitting data and a transmission control means for controlling drive timing of the reverse transfer means according to the output level of the CCD solid-state image sensor are respectively arranged.

(Due to the force action, according to the present invention, the G&TA load is transferred in the reverse direction during the horizontal blanking period in the light-receiving area in the light-receiving state, and by changing this reverse transfer timing, it becomes more optimal. The following exposure conditions can be obtained.

(f) Example Hereinafter, an explanation will be given according to an embodiment that illustrates the great invention.

This embodiment consists of a horizontal blanking pulse generation circuit (6) inputting a fixed generation circuit (5), a vertical blanking pulse generation circuit i71, and a first-second transfer lock generation port @(
81++o+ reverse transmission lock generation circuit (9) and horizontal transfer lock generation circuit (referred to above as river). The first transfer lock generation circuit (8) derives the vertical blanking pulse 1 transmission lock. 2nd transmission lock generation circuit +
]01 is a clock that transfers the accumulated charge # to the light receiving area (2) in the same way as the first vertical transfer lock during the vertical blanking period, and a clock that transfers the accumulated charge # in the light receiving area (2) to the entire one line during the vertical scanning period. A second transfer lock consisting of a horizontal register (31Ki!) is shifted in the vertical direction and transferred within the horizontal blanking period. A two-phase horizontal transmission lock is derived at 3.58 MHz, which causes the accumulated charge transferred to the horizontal register (3) to be derived in the next horizontal scanning period.The reverse feed lock generation circuit (9) is activated in the horizontal blanking period. A four-phase reverse feed lock is derived at 3.58 MHz.This reverse feed lock is the reverse phase of the vertical transfer tarlock issued during the vertical blanking period, and when applied to the electrode in the light receiving area (]). ,
The accumulated charges are transmitted in the opposite direction and flowed out to an overflow drain (not shown). Please note that this reverse feed lock is derived only during the horizontal blanking period in order to completely prevent noise from occurring in the image pickup output, and therefore, one transfer line is limited to 38 lines. Therefore, in this embodiment, the accumulated charges in all the light receiving areas (250 lines) are erased by continuing the reverse transfer seven times over seven horizontal opening periods.

The derived imaging output is processed in a video processing circuit (+2+ and derived as a video signal. This video signal deviation is partially integrated in an integration circuit 02). The integral output is
^ There is a correspondence relationship with the imaging output level, and fixing the integral output level to a predetermined value makes the exposure shape constant. The integrated output is sampled in the next stage sampling circuit 141 at vertical synchronization cycles. The sampling output is passed through a low-pass filter u5)t-1f- and inputted into an AD converter circuit, and the integrated output level with a small f value is converted into an AD converter. The reverse transfer pulse generation circuit (17) inputting this AD conversion data generates a reverse transfer pulse having a pulse width of 7 horizontal periods from the end t-starting point of the vertical blanking pulse.

Note that the reverse transfer pulse generation timing ij is delayed when the AD conversion data is large, and becomes early when it is small. The switching pulse generation circuit 0 is inputting the AND output (7 pieces) of the reverse transfer pulse and the horizontal blanking pulse to the tarok selection circuit 0 as a switching pulse. This clock selection circuit U9) selectively derives the reverse feed lock every time the H switching pulse is generated, so that the accumulated 4! At the timing of the reverse transfer pulse generation during the optical accumulation period, the L charge is reversely transferred by about 38 u·f every horizontal blanking period, and all the accumulated N! Charge is discharged outside the light receiving area. As a result, the accumulated charge transferred from the light-receiving area m to the storage area (2) becomes a charge 171 m1W after the reversal method, and the timing of generation of the reversal pulse completely controls the exposure amount.

FIG. 5 shows the first vertical shift lock (
It is a waveform explanatory diagram of g61) to (〆4). As is clear from the figure, during the photoaccumulation period, the vertical transmission lock (Ox) (cd2) of the first and second phases is at a high level state, and the charge generated by photoelectric conversion under the electrode. Save up. In addition, the first vertical transmission lock transfers the accumulated charge to the accumulation area during the vertical blanking period, and transmits it at the timing (tl) in the figure.
1) to (t4), the potential /V under the electrodes of the light receiving area (11) and the storage area (2) changes as shown in FIG.

Therefore, during the vertical blanking period, the accumulated charges are shifted in the forward direction (towards the accumulation area) as time passes. On the other hand, as is clear from FIG. 5, the 3.58 MHz reverse feed lock that occurs in response to the reverse transfer pulse that is derived by controlling the generation timing is caused by the clock selection circuit α9 corresponding to the reverse transfer pulse generation period. ) is derived from This reverse transfer tarlock occurs only during the horizontal granking period, as shown in FIG. 7, and the lock waveform is fully formed as shown in an enlarged view in FIG. 8. At timings (tl) to (t4) in FIG. 8, the corresponding '@electrode bottom y state changes as shown in FIG. 9. Therefore, during reverse transfer, the accumulated charges are transferred in the reverse direction over time and are discharged to the overflow drain.

Furthermore, g derived from the second transmission lock generation circuit (lO)
S2 vertical transfer lock CIzlsl ) ~(es4
)H1 As shown in FIG. 7, one charge is generated during the horizontal blanking period, and the accumulated charges are transferred to the horizontal register (3) one line at a time.

(g) According to the present invention, the reverse transfer timing changes according to the level of the video signal, and the reverse transfer is performed during the horizontal blanking period when horizontal transfer is not performed. Since only the above transfer is performed, the noise generated due to reverse transfer is not mixed into the VTL image output, and the effect is great.

4. Figure uTi (7J ia ql) Figure 1 is a circuit block diagram showing one embodiment of the present invention, Figure 2 is a diagram of a frame transfer type CCD solid-state image sensor @work E3A, and Figure 3 is a light accumulation period. 4 is an explanatory diagram of the conventional first vertical transfer lock waveform, FIG. 5 is an explanatory diagram of the first vertical transfer lock waveform of the present invention, and FIG. 6 is an explanatory diagram of the first vertical transfer lock waveform of the present invention. An explanatory diagram of potential changes during the ranking period, Fig. 7 is an explanatory diagram of the waveforms of the reverse feed lock and wJ2 vertical transfer lock, Fig. 8 is an explanatory diagram of the reverse feed lock waveforms, and Fig. 9 is the potential/I when the reverse rotation is completed. /Change explanatory diagram, respectively.

(1)...Light receiving area, (2)...Storage area, (
3)...Horizontal register.

Claims (1)

[Claims] (1) In a frame transfer type CCD solid-state image sensor, which transfers the accumulated charge in the light receiving area to the accumulation area during the vertical blanking period and derives the charge in the accumulation area in synchronization with a synchronization signal, the horizontal blanking period a reverse transmission means for transmitting the accumulated charge in the light receiving area in a direction opposite to the accumulation area; and a transfer control means for controlling the drive timing of the reverse transfer means according to the output level of the CCD solid-state image sensor. Exposure control circuit consisting of each.