JPS63244928A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of the offset voltage of an internal analog signal, by adjusting the current of a transistor(Tr) for power supplying by opening/closing a MOS Tr provided between an output terminal and a gate. CONSTITUTION:At a source follower circuit whose output terminal 4 is formed by the connection point of the Tr1 and Tr2, the Tr5 having a switching function is provided between the gate of the Tr2 and the output terminal 4, and also, a capacitor 6 for holding electric charge is provided between the gate and a ground terminal Vs. When the Tr5 is turned ON, an output voltage VS is stored in the capacitor 6. At this time, by setting the offset voltage at Voff. equation I can be obtained. Meanwhile, a general output voltage in the source follower circuit can be expressed in equation II, and generally, a constant G is set at around 20, therefore, the fluctuation of the voltage Voff can be improved to almost 1/20. Next, in the OFF state of the Tr5, since a constant voltage is stored in the capacitor 6, and a circuit goest to the source follower circuit, it is possible to reduce output impedance.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an output buffer circuit, and in particular to an analog MO
This invention relates to an output buffer circuit of an S integrated circuit.

(Prior Art) Generally, in an analog MOS integrated circuit, an internal analog signal is impedance-converted at its output section.
Output with low output impedance. As shown in FIG. 2, this internal analog signal is transmitted to, for example, a CCD
(Chargo CoupledDovlco), when the output is generated as a change from the reference signal level with an offset (of'fsct), the final output is based on the internal reference signal level due to the ease of signal processing in the external circuit. It is desirable to have an approximately constant offset amount regardless of the offset level of the signal.

A typical conventional output buffer circuit is shown in FIG. This circuit is composed of a MOS transistor and a current source 8 connected in series between a power supply terminal V and a ground terminal V8.The gate of the MOS transistor F is connected to the input terminal 3, and the gate of the MOS transistor F This is a source follower circuit in which the output terminal 4 is the connection point between the current source 8 and the current source 8.

In this type of source follower circuit, the current source 8 supplies current regardless of the magnitude of the offset voltage of the internal analog signal applied to the input terminal 3. Therefore, fluctuations in the offset voltage of the internal analog signal are directly reflected in the output voltage at the output terminal 4.

Therefore, the output processing circuit is required to deal with a wide range of offset voltage fluctuations of the analog signal, and thus becomes large and expensive.

(Problems to be Solved by the Invention) Conventional output buffer circuits reflect offset voltage fluctuations of internal analog signals as they are in the output voltage, so it has been reported that a large and expensive output processing circuit is required. was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output buffer circuit that suppresses fluctuations in the offset voltage of an internal analog signal so that the output processing circuit can be simplified and costs can be reduced.

[Structure of the invention]

(Means for Solving the Problems) The output buffer circuit according to the present invention includes a first MOS transistor whose gate is connected to an input terminal, whose source is connected to a first power supply terminal, and whose drain is connected to an output terminal. a second MOS transistor for current supply whose source is connected to the output terminal and whose drain is connected to the second power supply terminal; and a second MOS transistor provided between the output terminal and the gate of the second MOS transistor. and a charge holding capacitor inserted between the gate of the second MOS transistor and the second power supply terminal, and the voltage applied to the input terminal is lower than the reference voltage. It is characterized in that the third MOS transistor is made conductive during the period in which the MOS transistor is generated.

(Function) In the buffer circuit according to the present invention, the current supplied by the second MOS transistor is adjusted by opening and closing the third MOS transistor, thereby suppressing fluctuations in the output voltage in response to fluctuations in the level of the reference signal applied to the input terminal. At the same time, the signal at the input terminal is converted to a low output impedance and output.

(Embodiment) FIG. 1 shows a circuit diagram of an output buffer 7 circuit of an analog integrated circuit according to an embodiment of the present invention. This circuit consists of a driver MOS transistor 1 and a current supply MOS transistor 2 connected in series between a power supply terminal V and a ground terminal V, and the gate of MOS transistor 1 is connected to the input terminal. This is a source follower circuit that is connected to a terminal 3 and has an output terminal 4 at a connection point between MOS transistors 1 and 2. And M.O.S.
A MOS transistor 5 having a switch function is provided between the gate of the transistor 2 and the output terminal 4.
A charge holding capacitor 6 is provided between the gate of the S transistor 2 and the ground terminal 8.

Next, the operation will be explained. FIG. 2 is a graph representing an internal analog signal of an analog MOS integrated circuit, showing a reference signal level having a constant offset voltage and a signal component as a variation from that level. In FIG. 3(a), this signal repeats in time series, but the present invention is not limited thereto. Further, FIG. 3(b) shows the applied pulse φ for opening and closing the MOS transistor 5 in correspondence with the internal analog signal of FIG. 3(a). That is, during the generation period of the reference signal, the MOS transistor 5 performs an ON-OFF operation, and during the generation period of the signal as a change from the reference signal level, it is OFF.
It remains in the F state.

Now, the voltage applied to the gates of MOS transistor 1 and MOS transistor 2 is set to V.
and v2, the output voltage V3 at output terminal 4
is Habo* V −mV −G(V −V ) (1
). Here, v is the threshold voltage under the gate of the MOS transistor 2, m is the degree of modulation, and G is a constant determined by the shape and degree of modulation of the MOS transistor and MOS transistor 2.

First, when the MOS transistor 5 turns on, the output terminal 4 of the source follower circuit and the MOS transistor 2
The gate of is short-circuited, and the capacitance due to the output voltage 3 is stored in the capacitor 6. Now, the offset voltage of the internal analog signal applied to input terminal 3 is V. rf, during the period when the MOS transistor 5 is in the ON state, that is, during the period T shown in FIG. 3(b), vl ``Voff l (2)■2''''V3. Substituting into equation (1), the output voltage v3 is as follows.

On the other hand, in the conventional output buffer 7 circuit, a simple source
In the case of the follower circuit, its output voltage v3 is V3-Vo+mVorr (4). Here, Vo is a constant.

Comparing equations (3) and (4), it can be seen that in the output buffer circuit according to this embodiment, the offset voltage V. 2
．． When the output voltage (3) fluctuates, the fluctuation in the output voltage (3) is reduced to l/l+G compared to the conventional case. Normally, the constant G can be up to about 20, so the output voltage v3
is approximately 1/2 for the fluctuation of offset voltage vorr.
0 degrees of insensitivity. That is, the output buffer circuit according to this embodiment has an offset voltage of V. It is possible to improve the fluctuation of r' by more than one order of magnitude.

Next, when the MOS transistor 5 is turned off, the capacitance due to a constant voltage is stored in the capacitor 6. During the generation period of the signal as a change from the reference signal level, the capacitance stored in the capacitor 6 determines the current flowing through the MOS transistor 2, and the same operation as a normal source follower circuit is performed. , the internal analog signal applied to the input terminal 3 is impedance-converted and output with low output impedance.

As described above, according to this embodiment, it is possible to convert the internal analog signal into a low output impedance, and to suppress the variation in the offset voltage of the internal analog signal by approximately one order of magnitude. This makes it possible to simplify the output processing circuit and reduce costs.

〔Effect of the invention〕

As described above, according to the present invention, fluctuations in the reference signal level applied to the input terminal can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an output buffer circuit according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation thereof, and FIG. 4 is a circuit diagram showing a conventional output buffer 7 circuit. It is a diagram. 1.2.7...MOS transistor, 3...input terminal, 4...output terminal, 5...MOS switch, 6...
...Capacitor, 8...Current source, ■...Power supply terminal, v8...Ground terminal.

Claims (1)

[Claims] A first M, whose gate is connected to the input terminal, whose source is connected to the first power supply terminal, and whose drain is connected to the output terminal.
an OS transistor; a second MOS transistor for current supply whose source is connected to the output terminal and whose drain is connected to the second power supply terminal; between the output terminal and the gate of the second MOS transistor; a third MOS transistor provided in the input terminal; and a charge holding capacitor inserted between the gate of the second MOS transistor and the second power supply terminal, the voltage applied to the input terminal being a reference. An output buffer circuit characterized in that the third MOS transistor is made conductive during a period in which a voltage is being generated.