JPS63239827A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS63239827A JPS63239827A JP7140887A JP7140887A JPS63239827A JP S63239827 A JPS63239827 A JP S63239827A JP 7140887 A JP7140887 A JP 7140887A JP 7140887 A JP7140887 A JP 7140887A JP S63239827 A JPS63239827 A JP S63239827A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- stress relaxation
- relaxation agent
- stress
- stopper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 22
- 230000001681 protective effect Effects 0.000 claims abstract description 15
- 229920001296 polysiloxane Polymers 0.000 claims abstract description 10
- 239000003822 epoxy resin Substances 0.000 claims abstract description 6
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 6
- 229920002050 silicone resin Polymers 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 4
- 239000011347 resin Substances 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 abstract description 8
- 230000017525 heat dissipation Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 11
- 239000000919 ceramic Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、半導体チップがバ
ンプ電極を介して搭載基板に搭載される半導体装置に適
用して有効なものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and is particularly effective when applied to a semiconductor device in which a semiconductor chip is mounted on a mounting substrate via bump electrodes.
半導体チップをバンプ電極によってセラミックからなる
搭載基板に接続すると、それらの間の熱膨張差によって
バンプ電極に応力が加わる。そこで、搭載基板上の半導
体チップをセラミック等からなるキャップで封止した後
、このキャブ内にシリコーンゲルを充てんしてバンプ電
極に加る応力を緩和する技術が、日経マグロウヒル社発
行、日経エレクトロニクス、１９８４年９月２４日号、
ｐ、２６５〜ρ、２９３に記載されている。When a semiconductor chip is connected to a mounting substrate made of ceramic through bump electrodes, stress is applied to the bump electrodes due to the difference in thermal expansion between them. Therefore, a technology has been proposed by Nikkei Electronics, published by Nikkei McGraw-Hill, which seals the semiconductor chip on the mounting board with a cap made of ceramic or the like, and then fills the cap with silicone gel to alleviate the stress applied to the bump electrodes. September 24, 1984 issue,
p, 265-ρ, 293.
本発明者は、前記文献に記載されている技術を検討した
結果、次の問題点を見出した。As a result of studying the techniques described in the above-mentioned documents, the inventor found the following problems.
半導体チップをキャップで封止しているため。Because the semiconductor chip is sealed with a cap.
装置全体が大きくなり、また半導体チップにヒートシン
クを接して設けることができない。The entire device becomes large, and a heat sink cannot be provided in contact with the semiconductor chip.
本発明の目的は、半導体装置を小型にし、バンプ電極に
加る応力を緩和する技術を提供することにある。An object of the present invention is to provide a technique for reducing the size of a semiconductor device and relieving stress applied to bump electrodes.
本発明の他の目的は、半導体チップの放熱効果を上げ、
またバンプ電極に加る応力を緩和する技術を提供するこ
とにある。Another object of the present invention is to improve the heat dissipation effect of a semiconductor chip,
Another object of the present invention is to provide a technique for alleviating stress applied to bump electrodes.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体チップと搭載基板の間に応力緩和剤を
充てんし、さらに前記半導体チップの上面が露出するよ
うに、応力緩和剤の表面を樹脂からなる保護膜で覆った
ものである。That is, a stress relieving agent is filled between the semiconductor chip and the mounting substrate, and the surface of the stress relieving agent is covered with a protective film made of resin so that the upper surface of the semiconductor chip is exposed.
上述した手段によれば、半導体チップをキャップで覆わ
ないので、半導体装置が小型になりバンプ電極に加る応
力を緩和することができる。また。According to the above-described means, since the semiconductor chip is not covered with a cap, the semiconductor device can be made smaller and the stress applied to the bump electrodes can be alleviated. Also.
半導体チップを露出していることにより、ヒートシンク
を設けて半導体チップの放熱効果を上げることができる
。By exposing the semiconductor chip, a heat sink can be provided to improve the heat dissipation effect of the semiconductor chip.
以下１本発明の一実施例を図面を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は１本発明の一実施例の半導体装置の断面図であ
る。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
第１図において、１は単結晶シリコンからなる半導体チ
ップであり、半田等で形成した複数のバンプ電極２でセ
ラミックからなる搭載基板３に接続しである。バンプ電
極２には例えばｐｂが９５％、Ｓｎが５％の半田を用い
ている。バンプ電極２は、図示している以外に複数設け
られており、１個のバンブ電極２大きさは、それと半導
体チップ１の接している面の径が１００μｍ程度のもの
である。夫々のバンプ電極２は、半導体チップ１上の例
えばアルミニウム膜からなる配線及び搭載基板３上の例
えばアルミニウム膜からなる配線に接続している。搭載
基板３は、半導体チップ１が搭載されている面と反対側
の面にも半田からなるバンプ電極５を設けており、この
バンプ電極５でセラミックからなる実装基板４上の配線
に接続している。In FIG. 1, reference numeral 1 denotes a semiconductor chip made of single crystal silicon, which is connected to a mounting substrate 3 made of ceramic through a plurality of bump electrodes 2 formed with solder or the like. For the bump electrode 2, solder containing 95% PB and 5% Sn is used, for example. A plurality of bump electrodes 2 other than those shown are provided, and each bump electrode 2 has a diameter of about 100 μm at the surface in contact with the semiconductor chip 1. Each bump electrode 2 is connected to a wiring made of, for example, an aluminum film on the semiconductor chip 1 and a wiring made of, for example, an aluminum film on the mounting substrate 3. The mounting board 3 is also provided with bump electrodes 5 made of solder on the surface opposite to the surface on which the semiconductor chip 1 is mounted, and is connected to the wiring on the mounting board 4 made of ceramic with the bump electrodes 5. There is.
本実施例の半導体装置では、半導体チップ１と搭載基板
３および後述する保護膜８、ストッパ９で囲まれている
空間にシリコーンゲルからなる応力緩和剤７を充てんし
て、バンプ電極２と搭載基板３の間に加る応力、あるい
はバンプ電極２と半導体チップ１の間に加る応力を緩和
するようにしている。応力緩和剤７は、半導体チップ１
の側面及びヒートシンク６が設けられる上面は被覆して
いない、応力緩和剤７であるシリコーンゲルは、半導体
チップ１と搭載基板３の間に充てんした後。In the semiconductor device of this embodiment, a space surrounded by a semiconductor chip 1, a mounting substrate 3, a protective film 8, and a stopper 9, which will be described later, is filled with a stress relaxation agent 7 made of silicone gel, and the bump electrodes 2 and the mounting substrate are 3 or between the bump electrodes 2 and the semiconductor chip 1. The stress reliever 7 is applied to the semiconductor chip 1
After filling the space between the semiconductor chip 1 and the mounting substrate 3 with silicone gel, which is the stress relaxation agent 7, the side surfaces and the top surface where the heat sink 6 is provided are not coated.
１５０℃、１時間程度のキュアを行っている。搭載基板
３上には、半導体チップ１を囲むようにストッパ９が設
けられており、これによって応力緩和剤７であるシリコ
ーンゲルが、その充てん時に流れ出るのを防いでいる。Curing was performed at 150°C for about 1 hour. A stopper 9 is provided on the mounting substrate 3 so as to surround the semiconductor chip 1, and this prevents the silicone gel serving as the stress relaxation agent 7 from flowing out during filling.
ストッパ９は、ポリイミド層９Ａと、これの搭載基板３
側の面に銅層９Ｂを接着させて構成し、銅層９Ｂと搭載
基板３の間を例えば半田からなる接着剤１０によって接
着している。銅層９Ｂと半田層１０を用いることにより
。The stopper 9 includes a polyimide layer 9A and a mounting substrate 3 on which it is mounted.
The copper layer 9B is bonded to the side surface, and the copper layer 9B and the mounting board 3 are bonded together using an adhesive 10 made of, for example, solder. By using copper layer 9B and solder layer 10.
バンプ電極２のリフロ一時にストッパ９を搭載基板３に
取り付けることができるようにしている。A stopper 9 can be attached to the mounting board 3 during reflow of the bump electrode 2.
応力緩和剤７の半導体チップ１及びストッパ９から露出
している表面は、例えばシリコーン樹脂、エポキシ樹脂
等からなる保護膜８で覆って異物やイオンが混入するの
を防止している。保護膜８は。The surface of the stress reliever 7 exposed from the semiconductor chip 1 and the stopper 9 is covered with a protective film 8 made of silicone resin, epoxy resin, etc., to prevent foreign matter and ions from entering. The protective film 8 is.
半導体チップ１の周囲を囲むように設けられているため
、上から見るとリング状になっており、その外周部はポ
リイミド層９Ａの側面および上面の一部に接着している
。また、リング状になっている保護膜８の内周部は、半
導体チップ１の側面に被着している。保護膜８であるシ
リコーン樹脂あるいはエポキシ樹脂は、応力緩和剤７上
に被着して形成された後、１５０℃、１時間程度のキュ
アを行って硬化している。保護膜８から露出している半
導体チップ１の上面には、アルミニウム等からなるヒー
トシンクが接して設けられる。しかし、発熱量の小さな
半導体チップ１であれば、ヒートシンク６を設ける必要
はない。Since it is provided so as to surround the periphery of the semiconductor chip 1, it has a ring shape when viewed from above, and its outer periphery is adhered to a part of the side surface and top surface of the polyimide layer 9A. Further, the inner peripheral portion of the ring-shaped protective film 8 is adhered to the side surface of the semiconductor chip 1. The silicone resin or epoxy resin that is the protective film 8 is formed on the stress relaxation agent 7 and then cured at 150° C. for about 1 hour to harden. A heat sink made of aluminum or the like is provided in contact with the upper surface of the semiconductor chip 1 exposed from the protective film 8 . However, if the semiconductor chip 1 generates a small amount of heat, it is not necessary to provide the heat sink 6.
なお、接着剤１０としてシリコーンゴムを用いてもよい
。この場合には第２図に示すように、シリコーンゴムで
直接ポリイミド層９Ａを接着することができるので、ス
トッパ９の半田層９Ｂは不要である。なお、第２図は、
半導体装置の断面図である。Note that silicone rubber may be used as the adhesive 10. In this case, as shown in FIG. 2, the polyimide layer 9A can be directly bonded with silicone rubber, so the solder layer 9B of the stopper 9 is not necessary. In addition, Figure 2 shows
FIG. 2 is a cross-sectional view of a semiconductor device.
また、バンブ電極２の大きさ及び個数を限定する必要は
ないが、例えばバンブ電極２と半導体チップ１あるいは
搭載基板３との接着面積の総和が。Although it is not necessary to limit the size and number of the bump electrodes 2, for example, the total bonding area between the bump electrodes 2 and the semiconductor chip 1 or the mounting substrate 3 is limited.
半導体チップ１のバンプ電極１側の面の面積の１１５以
上になるようにしてもよい。このようにすることにより
、バンブ電極２に加る応力を小さくすることができる。The area may be 115 or more of the area of the surface of the semiconductor chip 1 on the bump electrode 1 side. By doing so, the stress applied to the bump electrode 2 can be reduced.
ここで、バンブ電極２の前記と異る構成について説明す
る。Here, a different configuration of the bump electrode 2 from the above will be explained.
第３図乃至第５図は、半導体装置を構成する半導体チッ
プ１及び搭載基板３の間の断面図である。3 to 5 are cross-sectional views between the semiconductor chip 1 and the mounting substrate 3 constituting the semiconductor device.
また、第３図に示すように、複数設けられるバンブ電極
２のうちの幾つかを、その他のバンブ電極２より例えば
２倍〜３倍程度大きなバンブ電極２Ａにしてもよい、こ
のようにすることにより、半導体チップ１とバンブ電極
２の間に加る応力、及びバンブ電極２と搭載基板３の間
に加る応力のそれぞれに対する耐久力を高めることがで
きる。Further, as shown in FIG. 3, some of the plurality of bump electrodes 2 may be made into bump electrodes 2A that are, for example, two to three times larger than the other bump electrodes 2. As a result, durability against stress applied between the semiconductor chip 1 and the bump electrode 2 and stress applied between the bump electrode 2 and the mounting substrate 3 can be increased.
また、第４図に示すように、半導体チップ１と搭載基板
３の間に充てんされている応力緩和剤７が外へ流れ出る
のを防止するために、半導体チップ１と搭載基板３の間
を電気的に接続するバンブ電極２と別に、半導体チップ
１の周辺部に接続しない半田バンプ２Ａを設けてもよい
。半田バンプ２Ａは、ｐｂが９８％、Ｓｎが２％からな
り、半導体チップｌと搭載基板３の間を接続するバンブ
電極２より大きくなっている。また、バンブ電極２は、
半導体チップ１と搭載基板３の間の熱膨張差を半導体チ
ップ１の周辺部で押え付けないようにするため、搭載基
板３から離されている。In addition, as shown in FIG. 4, in order to prevent the stress relaxation agent 7 filled between the semiconductor chip 1 and the mounting board 3 from flowing out, an electric current is applied between the semiconductor chip 1 and the mounting board 3. In addition to the bump electrodes 2 that are connected to each other, solder bumps 2A that are not connected to the periphery of the semiconductor chip 1 may be provided. The solder bumps 2A are made of 98% Pb and 2% Sn, and are larger than the bump electrodes 2 that connect between the semiconductor chip 1 and the mounting board 3. Moreover, the bump electrode 2 is
It is spaced apart from the mounting substrate 3 in order to prevent the difference in thermal expansion between the semiconductor chip 1 and the mounting substrate 3 from being suppressed by the periphery of the semiconductor chip 1.
また、第４図に示した半田バンプ２Ａは、第５図に示す
ように、搭載基板３側に設けるようにしてもよい。この
場合、半導体チップ１とは離されている。Furthermore, the solder bumps 2A shown in FIG. 4 may be provided on the mounting board 3 side, as shown in FIG. In this case, it is separated from the semiconductor chip 1.
以上説明したような構成から次の効果を得ることができ
る。The following effects can be obtained from the configuration described above.
（１）半導体チップ１と搭載基板３の間にシリコーンゲ
ルからなる応力緩和剤７を充てんし、また、応力緩和剤
７の流出を防止するストッパ９を設け。(1) A stress relaxation agent 7 made of silicone gel is filled between the semiconductor chip 1 and the mounting substrate 3, and a stopper 9 is provided to prevent the stress relaxation agent 7 from flowing out.
前記応力緩和剤７の表面をシリコーン樹脂、エポキシ樹
脂等からなる保護膜８で覆ったことにより。By covering the surface of the stress relaxation agent 7 with a protective film 8 made of silicone resin, epoxy resin, or the like.
半導体装置を小型にして半導体チップ１とバンブ電極２
の間の応力およびバンブ電極２と搭載基板３の間の応力
を緩和できる。また、異物やイオンの混入を防止できる
。The semiconductor device is made smaller and the semiconductor chip 1 and the bump electrode 2 are
The stress between the bump electrode 2 and the mounting substrate 3 can be alleviated. In addition, it is possible to prevent foreign matter and ions from entering.
（２）半導体チップ１の上面すなわちバンブ電極２が設
けられる面と反対側の面を露出していることにより、半
導体チップ１にヒートシンク６を設けることができる。(2) By exposing the upper surface of the semiconductor chip 1, that is, the surface opposite to the surface on which the bump electrode 2 is provided, the heat sink 6 can be provided on the semiconductor chip 1.
以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
半導体チップと搭載基板の間に応力緩和剤を充てんし、
また、応力緩和剤の流出を防止するストッパを設け、前
記応力緩和剤の表面を保護膜で覆ったことにより、半導
体装置を小型にして半導体チップとバンブ電極の間の応
力およびバンブ電極と搭載基板の間の応力を緩和できる
。また、異物やイオンの混入を防止できる。A stress reliever is filled between the semiconductor chip and the mounting board,
In addition, by providing a stopper to prevent the stress relaxation agent from flowing out and covering the surface of the stress relaxation agent with a protective film, the semiconductor device can be made smaller, reducing the stress between the semiconductor chip and the bump electrode, and reducing stress between the bump electrode and the mounting substrate. It can relieve the stress between. In addition, it is possible to prevent foreign matter and ions from entering.
また、半導体チップの上面を露出していることにより、
半導体チップにヒートシンクを設けることができる。In addition, by exposing the top surface of the semiconductor chip,
A heat sink can be provided on a semiconductor chip.
第１図は１本発明の一実施例の半導体装置の断面図、
第２図は、前記実施例の変形例を示した半導体装置の断
面図、
第３図乃至第５図は、半導体チップから搭載基板までの
断面図である。
図中、１・・・半導体チップ、２，５・・・バンプ電極
、２Ａ・・・半田バンプ、８・・・搭載基板（セラミッ
ク）、４・・・実装基板（セラミック）、６・・・ヒー
トシンク。
７・・・応力緩和剤（シリコーンゲル）、８・・・保護
膜（シリコーン樹脂、エポキシ樹脂）、９・・・ストッ
パ、
９Ａ・・・ポリイミド層、９Ｂ・・・銅層、１０・・・
半田層。
第 ３ 図
第４図
第 ５ 図 。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device showing a modification of the embodiment, and FIGS. It is a sectional view up to a mounting board. In the figure, 1... Semiconductor chip, 2, 5... Bump electrode, 2A... Solder bump, 8... Mounting board (ceramic), 4... Mounting board (ceramic), 6... heat sink. 7... Stress relaxation agent (silicone gel), 8... Protective film (silicone resin, epoxy resin), 9... Stopper, 9A... Polyimide layer, 9B... Copper layer, 10...
solder layer. Figure 3 Figure 4 Figure 5.
Claims (1)
した半導体装置であって、前記半導体チップと搭載基板
の間に応力緩和剤を充てんし、さらに前記半導体チップ
の上面が露出するように、前記応力緩和剤の表面を樹脂
からなる保護膜で覆ったことを特徴とする半導体装置。 ２、前記搭載基板の半導体チップが搭載されている側の
面に前記応力緩和剤の流出を防止するストッパが設けら
れていることを特徴とする特許請求の範囲第１項記載の
半導体装置。 ３、前記応力緩和剤は、シリコーンゲルからなることを
特徴とする特許請求の範囲第１項記載の半導体装置。 ４、前記保護膜は、シリコーン樹脂またはエポキシ樹脂
からなることを特徴とする特許請求の範囲第１項記載の
半導体装置。[Claims] 1. A semiconductor device in which a semiconductor chip is mounted on a mounting substrate via bump electrodes, wherein a stress relieving agent is filled between the semiconductor chip and the mounting substrate, and the upper surface of the semiconductor chip is A semiconductor device characterized in that the surface of the stress relaxation agent is covered with a protective film made of resin so as to be exposed. 2. The semiconductor device according to claim 1, wherein a stopper is provided on the side of the mounting substrate on which the semiconductor chip is mounted, to prevent the stress relaxation agent from flowing out. 3. The semiconductor device according to claim 1, wherein the stress relaxation agent is made of silicone gel. 4. The semiconductor device according to claim 1, wherein the protective film is made of silicone resin or epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7140887A JPS63239827A (en) | 1987-03-27 | 1987-03-27 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7140887A JPS63239827A (en) | 1987-03-27 | 1987-03-27 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63239827A true JPS63239827A (en) | 1988-10-05 |
Family
ID=13459656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7140887A Pending JPS63239827A (en) | 1987-03-27 | 1987-03-27 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63239827A (en) |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5111279A (en) * | 1989-08-28 | 1992-05-05 | Lsi Logic Corp. | Apparatus for isolation of flux materials in "flip-chip" manufacturing |
| US5168346A (en) * | 1989-08-28 | 1992-12-01 | Lsi Logic Corporation | Method and apparatus for isolation of flux materials in flip-chip manufacturing |
| US5249098A (en) * | 1991-08-22 | 1993-09-28 | Lsi Logic Corporation | Semiconductor device package with solder bump electrical connections on an external surface of the package |
| JPH05326625A (en) * | 1992-04-06 | 1993-12-10 | Nec Corp | Lsi mounting structure |
| JPH0661306A (en) * | 1992-08-12 | 1994-03-04 | Nec Corp | Chip carrier and its mounting structure |
| US5299730A (en) * | 1989-08-28 | 1994-04-05 | Lsi Logic Corporation | Method and apparatus for isolation of flux materials in flip-chip manufacturing |
| US5311060A (en) * | 1989-12-19 | 1994-05-10 | Lsi Logic Corporation | Heat sink for semiconductor device assembly |
| US5388327A (en) * | 1993-09-15 | 1995-02-14 | Lsi Logic Corporation | Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package |
| US5399903A (en) * | 1990-08-15 | 1995-03-21 | Lsi Logic Corporation | Semiconductor device having an universal die size inner lead layout |
| EP0623242A4 (en) * | 1992-01-24 | 1995-05-03 | Motorola Inc | Backplane grounding for flip-chip integrated circuit. |
| US5434750A (en) * | 1992-02-07 | 1995-07-18 | Lsi Logic Corporation | Partially-molded, PCB chip carrier package for certain non-square die shapes |
| US5438477A (en) * | 1993-08-12 | 1995-08-01 | Lsi Logic Corporation | Die-attach technique for flip-chip style mounting of semiconductor dies |
| US5489804A (en) * | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
| US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
| US5770889A (en) * | 1995-12-29 | 1998-06-23 | Lsi Logic Corporation | Systems having advanced pre-formed planar structures |
| US5834799A (en) * | 1989-08-28 | 1998-11-10 | Lsi Logic | Optically transmissive preformed planar structures |
| US6104093A (en) * | 1997-04-24 | 2000-08-15 | International Business Machines Corporation | Thermally enhanced and mechanically balanced flip chip package and method of forming |
| WO2000052739A3 (en) * | 1999-03-03 | 2001-01-11 | Intel Corp | A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material |
| US6528345B1 (en) | 1999-03-03 | 2003-03-04 | Intel Corporation | Process line for underfilling a controlled collapse |
| US6897094B2 (en) | 2002-03-11 | 2005-05-24 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US7141448B2 (en) | 1999-03-03 | 2006-11-28 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials |
| JP2007227609A (en) * | 2006-02-23 | 2007-09-06 | Seiko Epson Corp | Semiconductor device and manufacturing method of semiconductor device |
-
1987
- 1987-03-27 JP JP7140887A patent/JPS63239827A/en active Pending
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5111279A (en) * | 1989-08-28 | 1992-05-05 | Lsi Logic Corp. | Apparatus for isolation of flux materials in "flip-chip" manufacturing |
| US5168346A (en) * | 1989-08-28 | 1992-12-01 | Lsi Logic Corporation | Method and apparatus for isolation of flux materials in flip-chip manufacturing |
| US5834799A (en) * | 1989-08-28 | 1998-11-10 | Lsi Logic | Optically transmissive preformed planar structures |
| US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
| US5299730A (en) * | 1989-08-28 | 1994-04-05 | Lsi Logic Corporation | Method and apparatus for isolation of flux materials in flip-chip manufacturing |
| US5347162A (en) * | 1989-08-28 | 1994-09-13 | Lsi Logic Corporation | Preformed planar structures employing embedded conductors |
| US5489804A (en) * | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
| US5410805A (en) * | 1989-08-28 | 1995-05-02 | Lsi Logic Corporation | Method and apparatus for isolation of flux materials in "flip-chip" manufacturing |
| US5311060A (en) * | 1989-12-19 | 1994-05-10 | Lsi Logic Corporation | Heat sink for semiconductor device assembly |
| US5399903A (en) * | 1990-08-15 | 1995-03-21 | Lsi Logic Corporation | Semiconductor device having an universal die size inner lead layout |
| US5249098A (en) * | 1991-08-22 | 1993-09-28 | Lsi Logic Corporation | Semiconductor device package with solder bump electrical connections on an external surface of the package |
| EP0623242A4 (en) * | 1992-01-24 | 1995-05-03 | Motorola Inc | Backplane grounding for flip-chip integrated circuit. |
| US5434750A (en) * | 1992-02-07 | 1995-07-18 | Lsi Logic Corporation | Partially-molded, PCB chip carrier package for certain non-square die shapes |
| JPH05326625A (en) * | 1992-04-06 | 1993-12-10 | Nec Corp | Lsi mounting structure |
| JPH0661306A (en) * | 1992-08-12 | 1994-03-04 | Nec Corp | Chip carrier and its mounting structure |
| US5438477A (en) * | 1993-08-12 | 1995-08-01 | Lsi Logic Corporation | Die-attach technique for flip-chip style mounting of semiconductor dies |
| US5388327A (en) * | 1993-09-15 | 1995-02-14 | Lsi Logic Corporation | Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package |
| US5770889A (en) * | 1995-12-29 | 1998-06-23 | Lsi Logic Corporation | Systems having advanced pre-formed planar structures |
| US6104093A (en) * | 1997-04-24 | 2000-08-15 | International Business Machines Corporation | Thermally enhanced and mechanically balanced flip chip package and method of forming |
| WO2000052739A3 (en) * | 1999-03-03 | 2001-01-11 | Intel Corp | A controlled collapse chip connection (c4) integrated circuit package that has a filler which seals an underfill material |
| US6528345B1 (en) | 1999-03-03 | 2003-03-04 | Intel Corporation | Process line for underfilling a controlled collapse |
| US7141448B2 (en) | 1999-03-03 | 2006-11-28 | Intel Corporation | Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials |
| US6897094B2 (en) | 2002-03-11 | 2005-05-24 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| JP2007227609A (en) * | 2006-02-23 | 2007-09-06 | Seiko Epson Corp | Semiconductor device and manufacturing method of semiconductor device |
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