JPS63239544A - Memory protecting circuit - Google Patents

Abstract

PURPOSE:To securely a device complicate hold information stored in a RAM without making by writing through an AND gate to the RAM and closing the AND gate after a prescribed time passes. CONSTITUTION:When data are written into a RAM 7 and an address different from the address of the RAM 7 is accessed, a pulse signal is outputted from a NAND gate 13 to a DFF 11. Thus, a writing signal is outputted from the output edge of an AND gate 9 to the RAM 7 and the data is written. Here, when a prescribed time by the time constant of a delaying circuit 15 passes, the DFF 11 is reset, the gate 9 is closed and the supply of the writing signal to the RAM 7 is stopped. Consequently, at the time of the runaway of a CPU 1, the destruction of the address of the RAM 17 can be prevented. Thus, without making the device complicate, the information stored in the RAM can be held without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory protection circuit that prevents data stored in a memory from being destroyed.

(Prior Art) In recent years, with the rapid development of memory IC technology, ROM and RAM of this memory IC are being used in various devices. FIG. 3 is a configuration diagram showing an example in which ROM and RAM are applied to a power consumption measurement storage device. In the same figure,
Measurement storage device 33ucpυ (central processing unit f)1. R.O.
M3. The configuration consists of a RAM 7, a measurement interface 37, and a data bus. This measurement storage device 33 measures the measurement pulses inputted from the electricity meter 35 at predetermined time intervals (for example, 30 minutes) using a total of one interface 37, and then outputs the measurement pulses via the data bus according to the control signal from the CPU 1.
The information is stored sequentially at a predetermined address of AM7. Since the data stored in the RAM 7 is retained for a long period of time, for example - years, it is not easy to reliably protect the data during that period.

(Problem to be solved by the invention) In the conventional device, the data of the measured electric energy is
It was to be stored in the M7 for a long time.

However, since data can be replaced in RAM 7, which stores data for a long period of time, if a runaway occurs in the control program of CPtJl, for example, the address of RAM 7 changes from 2000 (H) → 2001 (H) → 2002 (H
) and then destroyed, destroying the extensive data that has been stored for a long time. As a countermeasure for this, C.
It is conceivable to provide the PU1 with a supervisory control circuit having a counter, a register, etc. to monitor the control program.
Providing this supervisory control circuit would complicate the device and increase maintenance costs, and a countermeasure for this problem has been desperately needed.

The present invention has been made in view of the above, and as a countermeasure thereof, it is an object of the present invention to provide a memory protection circuit that can reliably retain information stored in a memory without complicating the device.

[Structure 1 of the Invention (Means for Solving the Problems) In order to achieve the above object, the present invention provides address access means for accessing different addresses of a replaceable memory when writing information to the memory. and write request means for outputting an information adjustment request signal upon access by the address access means; a write request signal from the write request means and a write command signal for instructing writing of information to the memory. write signal output means for outputting a J11 signal to the memory based on the logical product of the above, and outputting a stop signal for causing the write request means to stop outputting the write request signal after a predetermined time has elapsed since access by the address access means. The gist is to have a write control means.

(Operation) When writing information to the memory using the memory protection circuit with the above configuration, when the address access means accesses a different address in the memory where the information can be replaced, a write request signal is generated from the write request means. The write signal output means outputs a write signal to the memory based on the logical product of this write request signal and a write command signal that instructs writing of information to the memory, and the address access means accesses the memory. The purpose of the present invention is to cause the loading control means to stop outputting the write request signal from the write request means after a predetermined period of time has elapsed.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the memory protection circuit of the present invention.

Its feature is that when writing data to RAM7, R
When an address different from the address of AM7 is accessed, a pulse signal is output from the Nant gate 13 to the D-flip 70 knob 11, and the output terminal of this D-flip-flop 11 and the write terminal of the CPU 1 go to O-level, so that the AND The write signal from the output terminal of gate 9 is RA
Output to M7. When a write signal is output to the RAM 7, data is written to the address written in the RAM 7 by the CPU 1 via the data bus. When 1 byte of data is written to RAM 7, D flip 7O from delay circuit 15
By inputting a reset signal to the clear terminal of the knob 11, the AND gate 9 performs a logical sum and the writing is completed.

This is different from the conventional device in that data is written into the RAM 7 while opening and opening the output terminal of the AND gate 9.

The configuration of this embodiment having the above functions is CPLJI.

ROM3. RAM5 and RAM7, an AND gate 9 as a protection circuit, and a D flip 70 tube 11 connected to this AND gate 9. Nant gate 13 and a delay circuit 15 connected to this D flip-flop 11
．． It has an AND gate 17 and an OR gate 19.

The CPU 1 receives address signals Ao to A11 and a data bus,
It has a read terminal and a write terminal, each with RO
M3. It is connected to RAM 5 and RAM 7 to control successive output or writing of data in RAM and the like.

RAM7 is for storing long-term data, and is
The address signal A o - A n % data bus, read terminal, and write terminal of pui are connected to this 8-in terminal via an AND gate 9, which will be described later, and a write signal is input from this AND gate 9. When address signal AO~A
Data is written to n accessed addresses.

The Nant gate 13 is connected to the address signal AO~ of CPtJl, and the address signal AO~An I of CPUI
An address different from the address of fiRAM7, for example, ROM3. When an address in the RAM 5 or an address in the memory address space is accessed, the output terminal changes from a low level to a high level, thereby outputting a pulse signal to the D flip 70 tube 11.

The input terminal of the D flip-flop 11 is a Nant gate 13
On the other hand, the output terminal Q is connected to the input terminal of the AND gate 9, the output terminal Q is connected to the input terminal of the AND gate 17, and a pulse signal is input from the output terminal of the Nands gate 13. Then, the output terminal Q becomes a high level and the output terminal Q becomes a low level, thereby causing the input terminal of the AND gate 9 to become a low level.

In addition, the clear (CLR) terminal is connected to the delay circuit 15, and when a clear signal is input from the delay circuit 15, it enters the reset state, and when the D-flip occurs, the output terminal Q of the block flop 11 becomes low level and the output terminal Q becomes high level. This causes the input terminal of the AND gate 9 to be at a high level.

The delay circuit 15 has a resistor and a capacitor, and one end of the resistor has the write terminal and read terminal of CPLJl as input terminals, the output terminal of an OR gate 19, and the output terminal Q of the above-mentioned D flip-flop 11 as input terminals. It is connected to the output terminal of the AND gate 17, and the other end is the clear (CLR) of the D flip-flop 11 along with the capacitor.
connected to the terminal. This delay circuit 15 clears the clear terminal after a time constant (fRC) of the square root of the product of the resistor and the capacitor after the output terminal Q of the D flip-flop 11 becomes high level and the output terminal of the AND gate 17 becomes high level. The D-flip 70 knob 11 is brought into a reset state through the D-flip 70 knob 11. This time constant 7RC stores 1 byte of data in RAM.
This is the so-called machine cycle required to write to 7.

One end of the input terminal of the AND gate 9 is connected to the write terminal of the CPU 1, and the other end is connected to the output terminal Q of the D flip-flop 11.
When the write terminal and the output terminal Q become low level due to the logical product with the output terminal Q of the knob 1, the write signal WR is supplied to the m superstition 9 terminal of the RAM 7.

ROM3 sends the stored data to address signal 5Ao-
It is supplied to the CPU 1 via the data bus upon access by An.

RAM5 accesses address signals Ao to An.

When the read signal RD is input to the address to be read, stored data is supplied to the CPU 1 via the data bus, and when the write signal WD is input, the data is written from the CPU 1 via the data bus. It is.

Next, the operation of this embodiment will be explained.

First, when writing data to the RAM 7 after the system is powered on, the write terminal of the CPUI becomes low level, and at the same time the input terminals of the AND gate 9 and the off gate 19 become low level, the RAM 7 is written by the address signals AO to An. When an address different from the address is accessed, a pulse signal is output from the output terminal of the Nant gate 13 to the D flip 70 knob 11. And CPLJl
accesses the address to write data to address signal @ via ○~All. When a pulse signal is input, the output terminal Q of the D flip-flop 11 changes from high level to low level, and the input terminal of the AND gate 9 changes to low level. Further, as the output terminal Q changes from low level to high level, the input terminal of AND gate 17 becomes high level, and furthermore, since the output terminal of OR gate 19 is at high level, the output terminal of AND gate 17 also becomes high level. Then, when the logical product of the AND gate 9 becomes low level, the output terminal becomes low level and RA
By supplying a write signal to the write signal end of M7,
Data is written to the address accessed via the data bus. After the time constant fRC has elapsed since accessing a different address in RAM 7, the delay circuit 15 activates the D flip 7O.
D flip 70 via the clear terminal of knob 11
is reset and the output terminal Q changes from a low level to a high level, so that the output terminal of the AND gate 9 goes to a high level and the write signal WR is no longer supplied to the write t3@ end of the RAM 7. This operation transfers 1 byte of data to RAM.
Repeated every time 7 is written.

As a result, when writing data to RAM7, 1
Since the output terminal of the AND gate 9 is opened and closed every time a byte of data is written, it is possible to prevent the address of the RAM 7 from being destroyed even when the CPLJl control program is running.

Furthermore, the circuit of this embodiment is a simpler circuit than providing a supervisory control circuit in the CPU 1, so it can be manufactured at low cost.

FIG. 2 is a configuration diagram showing another embodiment, and its features include the RAM5 and RAM7 in the above embodiment.
Byte (8 bytes
2000 (H) to 2 F out of H) to 3FFF (H)
The reason is that the area up to FF' (H) is used as an area for storing important data, and data is written by accessing the address signals A12 and At3.

When writing data to 2000 (H) to 2FFF (H) of this RAM 27, write data from address signal A12 e At 3 to 2000 (H) of RAM 27 in the same manner as in the above embodiment.
By accessing an address other than 00 (H) to 2FFF (H), the output terminal of the Nante gate 31 becomes low level, one end of the input terminal of the AND gate 23 becomes low level, and the input terminal of the other end becomes Included signal W
The input of R causes the output terminal of the AND gate 23 to become low level due to the logical product, so that a write signal is supplied from the output terminal of the OR gate 25 to the write signal end of the RAM 27, and writing is performed.

Thereby, by specifying the address of the data area of the RAM 27, it is possible to prevent data destruction due to runaway of the CPU 1, etc., as in the above embodiment.

[Effect of the Invention 1] As explained above, according to the present invention, when information is written into a memory that can be replaced, a write request signal output by accessing a different atris of this memory and a write request signal output from the memory Writing to the memory is performed by ANDing with a write command signal that commands writing of information, and the output of the write request signal is stopped after a predetermined period of time has elapsed from accessing a different address in the memory, making the device complicated. It is possible to reliably retain information stored in memory without having to

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the memory protection circuit of the present invention, FIG. 2 is a circuit diagram of another embodiment of the invention, and FIG. 3 is a circuit diagram of a conventional example. 1...CPU 5.7...-RAM 9...AND gate 11.29...D flip 70 knob 13.31...NAND gate 15...Delay circuit 17.21.23... AND gate 19.25...OR gate

Claims (2)

[Claims] (1) address access means that accesses a different address in the memory when writing information to a replaceable memory; write request means that outputs an information write request signal upon access by the address access means; write signal output means for outputting a write signal to the memory by a logical product of the write request signal from the write request means and a write command signal for instructing writing of information to the memory; and the address access means. write control means for outputting a stop signal for causing the write request means to stop outputting the write request signal after a predetermined period of time has elapsed since access to the memory protection circuit. (2) The memory according to claim 1, wherein the write control means outputs a stop signal to the write request means after 1 byte of information is written to the memory. protection circuit.