JPS63237295A - Monvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the rewrite time of an E<2>PROM, while preventing a breakdown at the time of erasion, by setting an erase voltage applied to a rewrite electrode to a smaller voltage than a write voltage. CONSTITUTION:One cell in a memory cell array 1 which has been brought to a two-dimensional array is selected by a decoder 2 and 3. In this case, the decoder 2 and the decoder 3 select a rewrite electrode EG of the cell, and a control gate CG, respectively. A boosting circuit 4 is a circuit for generating a higher program voltage Vp than an external power source potential, and an operation mode switching circuit 5 is a circuit for outputting the voltage Vp to one of nodes N1, N2 at the time of write and at the time of erasion. That is, at the time of write, the voltage Vp is outputted to the node N1, and it is applied as a write voltage VCG to the control gate CG selected by the decoder 3. At the time of erasion, the voltage Vp is outputted to the node N2, but in this case, the voltage Vp is lowered to a low voltage by a voltage control circuit 6, and applied as an erase voltage VEG to the rewrite electrode selected by the decoder 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device that has a floating gate and allows electrical rewriting of each memory cell.

(Prior art) As a non-volatile semiconductor memory device (E2 FROM) which has a MOS transistor structure with a floating gate and a control gate and allows information content to be electrically and selectively rewritten, the non-volatile semiconductor memory device (E2 FROM) shown in FIG. Memory cells represented by equivalent circuits are known. This memory cell has a source region S formed on a semiconductor substrate.

A floating gate FG is provided on the channel region between the drain regions via a gate insulating film, and a control gate CG is further provided on this via a gate insulating film. A rewrite electrode EG is provided in the substrate by a diffusion layer separately from the channel region, and the rewrite electrode EG is opposed to the floating gate FC via an extremely thin insulating film through which a tunnel current can flow.

E2 FROM is a memory cell in which such memory cells are arranged in a matrix on a substrate, and a high voltage generation circuit is formed inside to enable selective rewriting of each memory cell.
is configured.

The selective read and rewrite operations of the E2 FROM will be explained below, taking an n-channel example as an example.

First, to write information to a selected memory cell, the rewrite electrode EG is kept at a low potential (for example, OV), and the control gate CG is supplied with a boosted high-potential program voltage Vp (for example, 20V) from an internal high voltage generation circuit. is given as the write voltage. As a result, electrons are injected from the rewrite electrode into the floating gate FG by a tunnel current through the extremely thin insulating film.

If the state where no charge is injected into the floating gate and the threshold value is a small positive value is "0", then electrons are injected into the floating gate by this write operation and the threshold value becomes a large positive value. The current state is "1".

In the read operation, a read voltage (eg, 5V) is applied to the drain D and control gate CG of the selected memory cell, and all other electrodes are set to a low potential (eg, OV). At this time, if this memory cell is 0#, a channel current flows, and if this memory cell is "1", no current flows. Depending on the presence or absence of this channel current, a determination is made between "0" and "11".

To erase the contents of a memory cell, do the opposite of writing.
The control gate CG is kept at a low potential (for example, OV), and the above-mentioned program voltage Vp is applied to the rewrite electrode EG as an erase voltage. At this time, the electrons in the floating gate FG are released to the rewrite electrode EC through the extremely thin insulating film, and the memory cell becomes "0".
"become.

In such a conventional E2 PROM, the time required for rewriting becomes shorter as the above-mentioned program voltage Vp is increased.

However, if the program voltage Vp is made too high, when erasing information, this program voltage Vp is applied to the rewriting electrode, which is a diffusion layer in the substrate, resulting in junction breakdown or surface breakdown in this part, making rewriting impossible. .

Therefore, the program voltage Vp could not be made too high, and as a result, the rewriting time could not be shortened sufficiently.

(Problems to be Solved by the Invention) As described above, in the conventional E2 FROM, the program voltage used for rewriting is one type, so if you try to shorten the rewriting time by increasing the program voltage, the withstand voltage will increase. There was a problem with not having it.

The present invention solves these problems. The purpose is to provide E2 FROM.

[Structure of the Invention] (Means for Solving Problems) In the E2 FROM of the present invention, the erase voltage applied to the rewrite electrode is set to a smaller value than the write voltage applied to the control gate.

(Function) According to the present invention, by differentiating the write voltage and the erase voltage, breakdown during erasing can be prevented while
2. The time required to rewrite FROM can be shortened.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of an E2 FROM of one embodiment.

The memory cells are as shown in the equivalent circuit in FIG. 2, and constitute a memory cell array 1 in which these are arranged in a matrix. Decoders 2 and 3 are for selecting one of the two-dimensionally arranged memory cells, and here the decoder 2 selects the rewrite electrode EC of the memory cell,
Decoder 3 selects control gate CG. The booster circuit 4 is a circuit that generates a program voltage Vp higher than the external power supply potential, and the operation mode switching circuit 5 changes the program voltage Vp to the nodes N1, . This is a circuit for switching which of N2 to output. That is, during writing, the program voltage Vp is output to the node N1, and this is applied to the control gate CG selected by the decoder 3 as the write voltage VCC. Program voltage V during erasing
p is output to node N2. The program voltage Vp outputted to the node N2 is lowered by a predetermined value by the voltage control circuit 6 and applied to the rewrite electrode selected by the decoder 2 as the erase voltage VEG.

Writing and erasing operations in the E2 FROM of this embodiment will be explained with reference to FIGS. 3 and 4.

In these figures, the white part is "VALID", and the shaded part is DON.
T CARE”.

In the information write mode, as shown in Figure 3, ADDR
ESS, write enable WE.

When DATA IN is set and the chip enable CE goes to the "L2 level", a write voltage VCG of 20V is output and applied to the control gate CG of the selected memory cell. At this time, the voltage of the rewrite electrode EC is OV. As a result, in the selected memory cell, electrons are injected from the rewriting electrode EG into the floating gate FG, and writing is performed.

In the information erase mode, as shown in FIG. 4, the ADDRES S, write enable WE,
When DATA IN is set and the chip enable goes low, an erase voltage VEG-17V is output and applied to the rewrite electrode EG of the selected memory cell. At this time, the voltage of the control gate CG is 0■.

As a result, in the selected memory cell, the floating gate (FG)
The electrons stored in the memory are emitted to the rewrite electrode EG due to the tunnel effect, and erasing is performed.

Thus, in this embodiment, the erase voltage applied to the rewrite electrode made of the diffusion layer in the substrate is set to a smaller value than the write voltage applied to the control gate. Therefore, breakdown during erasing can be reliably prevented while reducing the write time by setting the write voltage to a sufficiently high value.

Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, the E2 PROM is designed to shorten the write time while preventing breakdown during erasing by differentiating the write voltage and the erase voltage.
Can you get it?

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an E2 FROM according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of its memory cell, and FIG.
The figure is a timing diagram in the write mode, and FIG. 4 is a timing diagram in the erase mode. 1...Memory cell array, 2, 3...Decoder, 4
... Boost circuit, 5... Operation mode switching circuit, 6...
・Voltage control circuit, D...drain, S...source,
EG...Rewriting electrode, FC...Floating gate, CG...
...Control gate, VCa...Write 7 high pressure, VEQ.
...Erasing voltage. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] A memory cell having a floating gate is integrated on a semiconductor substrate and has a high voltage generation circuit inside, and each memory cell has a source and a drain region formed apart from each other on the semiconductor substrate, and A floating gate formed on a channel region between regions via a gate insulating film, a rewrite electrode installed opposite to this floating gate via an extremely thin insulating film, and installed capacitively coupled to the floating gate. and a control gate, and sets a potential relationship between the control gate and the rewriting electrode for the selected memory cell, and transfers electric charge between the rewriting electrode and the floating gate, thereby controlling the electrical content of the stored content. In a non-volatile semiconductor memory device that enables permanent rewriting, the erase voltage applied to the rewriting electrode during erasing to release charges from the floating gate is higher than the write voltage applied to the control gate during writing to inject charges to the floating gate. A nonvolatile semiconductor memory device characterized in that the value is set to a low value.