JPS63236354A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an LSI composed of MOS FETs, and more particularly to a semiconductor device equipped with an internal power supply voltage drop-down circuit.

(Prior art) -12, LSI configured using MOS FET
, all MOS FETs in the LSI chip
The gate oxide film thicknesses are set to be the same. This is because the manufacturing process is the simplest and all MOS FETs in the 81 chip operate at 5V.

However, as LSIs have become more highly integrated in recent years, each element and wiring have become increasingly finer, and design rules have become less
．． When it becomes 8μm or less, the operating power supply voltage of 5■ above is LS.
It is becoming difficult to maintain the reliability of I. this is,
This is because the electric field becomes higher when the device is reduced in size while keeping the power supply voltage constant.

As a result, problems such as hot carrier effects and breakdown voltage deterioration of the gate oxide film arise.

As a countermeasure against this problem, it is possible to make the MOS FET have an LDD structure so as to make it resistant to hot carriers, but this also has its limits, and there is no definitive measure against deterioration of the breakdown voltage of the gate oxide film.

In view of the above-mentioned circumstances, methods have been proposed for lowering the internal power supply voltage of LSIs. In this system, a power supply voltage of 5V is supplied from the outside, this power supply voltage is lowered to approximately 3.3V by a power supply voltage drop circuit formed within the chip, and the internal circuit is operated with this lowered voltage. . However, even with such a configuration, there is a circuit in the input/output section that operates at 5.times., and hot carrier effects in this circuit and deterioration in the withstand voltage of the gate oxide film are unavoidable.

(Problems to be Solved by the Invention) As mentioned above, conventional semiconductor devices have drawbacks such as hot carrier effects and gate oxide film breakdown voltage deterioration due to higher integration, resulting in lower LSI reliability. be. In order to eliminate these drawbacks, it has been considered to make the MO'S FET an LDD structure, but this also has its limitations.
Moreover, deterioration of the breakdown voltage of the gate oxide film cannot be prevented. Therefore, methods have been proposed to lower the internal voltage of the LSI, but even with such a configuration, hot carrier effects in the input/output circuit and deterioration of the breakdown voltage of the gate oxide film cannot be avoided.

This invention was made in view of the above circumstances,
The purpose is to provide a semiconductor device that can reliably reduce hot carrier effects and breakdown voltage deterioration of a gate oxide film and improve reliability even when miniaturized due to high integration.

[Structure of the invention] (Means and effects for solving the problem) In other words, in this invention, in order to achieve the above object, a MOS
Two or more types of FET gate oxide films are used inside the LSI, and the gate oxide film thickness of MOS FETs in the input/output circuit section operated by externally supplied power supply voltage is determined by the voltage dropped by the power supply voltage drop circuit. The gate oxide film is formed thicker than the gate oxide film of the MOS FET in the internal circuit operated by the MOS FET.

By doing this, the MOS in the input/output circuit section
The gate insulating film of the FET is thick, which prevents hot carrier effects and deterioration of the withstand voltage of the gate oxide film, and the power supply voltage drop circuit reduces the voltage supplied to the internal circuit, making it possible to reduce the voltage supplied to the internal circuit of the MOS FET. The gate oxide film thickness may be thin, without hindering high integration or degrading performance.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 2 shows an example of a circuit configuration of a semiconductor device having a power supply voltage drop circuit. In Figure 2, 11 is L
This chip 11 is an SI chip, and the chip 11 includes an input/output circuit section 12 that operates with a power supply voltage of 5 cm and exchanges data with the outside.
A power supply voltage drop circuit 13 that drops the 5V power supply voltage supplied via this input/output circuit section 12 to, for example, 3.3V.
, and a cell and peripheral circuit 14 that are operated by being supplied with the voltage dropped by the power supply voltage drop circuit 13.

FIG. 1 shows a cross-sectional configuration of MOSFETs forming the input/output circuit section 12 and the cell and peripheral circuits 14 in the circuit shown in FIG. In FIG. 1, 15 is a P-type silicon substrate, 16 is an N-type well region to which a voltage of 3.3V is applied, 17 is an N-type well region to which a voltage of 5V is applied, and 18 is a film thickness. 12 nm gate oxide film, 19 is a gate oxide film with a film thickness of 20 nm, 20.20- is a source region, 21.21- is a drain region, 22 is a gate electrode, 2
3 is an oxide film for element isolation, and as shown in the figure, the input/output circuit section 1
The gate oxide film 19 of the MOS FET 2 constitutes
It is formed thicker than the gate oxidation layer 18 of the MOS FET constituting the cell and peripheral circuit 14.

Next, a method for manufacturing a semiconductor device having the above-described structure will be described with reference to FIGS. 3(a) to 3(d).

First, as shown in FIG.
6.17 is formed. Next, after selectively forming an oxide film 23 for element isolation, a gate oxide layer G1 is formed on the silicon substrate 15 on the element region separated by this oxide film 23 for element isolation.
24 is formed to have a thickness of about 12 nm.

Next, the gate insulating film 24 of the MOSFET constituting the cell and peripheral circuit 14 is selectively etched and removed to expose the silicon substrate 15, as shown in FIG.

After that, thermal oxidation is performed again to form a film with a thickness of about 12 nm on the exposed silicon substrate 15 of the cell and peripheral circuit 14.
A gate oxide film 18 is formed. At this time, the gate oxide gI24 of the input/output circuit section 12 grows into a gate oxide film 19 with a thickness of about 20 nm, as shown in FIG.

The subsequent steps are similar to normal CMOS processes. After forming the polysilicon gate 22, using the polysilicon gate 22 as a mask, ions of impurities forming N-type and P-type are selectively implanted to form an N-channel. Type M
Source region 20' and drain region 21-1 of O3FET
and the source region 20 of the P-channel MO3FET. Drain regions 21 are formed respectively (as shown in the figure (d)).

According to such a manufacturing method, the gate oxide film 19 of the MOS FET of the input/output circuit section 12 that operates at 5.
It can be made thicker than the gate oxide film 18 of SFET. In such a configuration, the MOS forming the input/output circuit section 12
FETs can prevent hot carrier effects and breakdown voltage deterioration of the gate oxide film by having a thick gate oxide film, and the cell and peripheral circuit 14 can prevent hot carrier effects and breakdown voltage degradation of the gate oxide film by lowering the electric voltage. The MOSF of the entire circuit constituting the LSI chip 11 can be prevented.
The reliability of ET can be greatly improved. For example, as in the embodiment described above, the MOS F constituting the input/output circuit section 12
When a voltage of 20nrrrr5V is applied to the gate oxide film 19 of the ET, the electric field applied to the gate oxide film of this MOSFET is 2.5MV/cm, and the cell and peripheral circuit 1
The gate oxide film 18 of the MOSFET constituting 4 is 12n
When a voltage of 3°3V is applied at m, the electric field is 2.75
MV/cm, and both have an electric field of 3 to 5 MV/cm or less, which is generally said to be able to guarantee reliability, and sufficiently high reliability can be obtained.

Furthermore, in the configuration of the present invention, since 5.5 can be used as an LSI interface, it is possible to use the conventional TTL compatibility without breaking down.

[Effects of the Invention] As explained in the first paragraph, the present invention provides a semiconductor device that can reliably reduce the hot carrier effect and breakdown voltage deterioration of the gate oxide film and improve reliability even when miniaturized due to high integration. I'm disappointed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a circuit configuration of the device shown in FIG. 1, and FIG. 3 is a diagram showing the circuit configuration of the device shown in FIG. FIG. 3 is a diagram for explaining a method for manufacturing a semiconductor device. 11... LSI chip, 12... Input/output circuit section, 1
3...Power supply voltage drop circuit, 14...Cell and peripheral circuit, 18...MOS constituting the cell and peripheral circuit
Gate oxide film of FET, 19... Gate oxide film of ~10 SFET constituting the input/output circuit section.

Claims (1)

[Claims] In a MOS type semiconductor device equipped with a power supply voltage drop circuit, an M operating based on an externally supplied power supply voltage is used.
The gate insulating film thickness of the OSFET is adjusted based on the voltage dropped by the power supply voltage drop circuit.
A semiconductor device characterized in that it is formed thicker than a gate insulating film of an ET.