JPS63234720A - Resetting circuit - Google Patents

Abstract

PURPOSE:To securely generate a resetting signal without being influenced by the rise characteristic of a power source voltage by connecting in a multistage and cascade way a resistance load type source ground circuit stage and a capacity load type source ground circuit. CONSTITUTION:Transistors Tr1, 3 and 2 for driving of respective stages are respectively of an enhancement form and have a threshold value voltage. By connecting the drain of a Tr1 and a gate, the rise of the output contact voltage of a source grounding circuit 51 is delayed compared with the rise a power source voltage Vdd. An output contact (a) starts the voltage rise after the power source voltage exceeds the threshold voltage. In the same way, at an output point (b) of a source grounding circuit 52, the rise is delayed by the threshold voltage of Tr1 and Tr3 only. The rise of the output voltage of an output contact (c) of a source grounding circuit 53 is delayed only by the time constant of the integrating circuit composed of the sum of the delaying of respective threshold voltages of Tr1 and 3, Tr2 and a capacity 8. The output voltage of the circuit 53 is inputted to a Schmidt trigger and converted to binary information having hysteresis.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to a power-on reset circuit of a semiconductor device.
Illll. For example, the present invention can be applied to M OS l! I 1
Used in 01 path elements.

[Prior Art] A power-on reset circuit is known that prevents malfunctions of electronic circuits that occur when the Wt power supply voltage rises. The power-on reset circuit generates a control signal with a delay from the rise of the power supply voltage, and the control signal controls the output stage, such as the first stage of the display driver, to prevent erroneous display or malfunction. .

As can be seen from the above explanation, the power-on reset circuit has a delay circuit function that delays the rising waveform of the JR voltage by a predetermined period of time, and converts the rising waveform into a binarized signal of a predetermined level. It has both non-linear circuit functions to convert.

In order to achieve the above circuit function, enhancement type M
Power-on reset circuits with common source circuits using OS transistors as drivers have already been proposed.

For example, Japanese Patent Application Laid-Open No. 1986-208621 proposes a MOS power-on reset circuit that uses a capacitor as a load element of the first-stage common source circuit.

The output contact of the first source-grounded circuit stage sends an output signal voltage to a CMOS inverter stage loaded with a second capacitor, and the output voltage of the CMOS inverter stage is further converted into a binary value by an inverter serving as a comparator to control the output. voltage.

In the prior art described above, the rise of the output voltage of the first stage common source circuit is delayed due to the charging/discharging time constant of the MOS transistor and its load capacitor.

The operation of the second stage CMOS inverter circuit having a capacitive load is also basically the same as the first stage common source circuit.

Therefore, it is understood that the MOS power-on reset circuit disclosed in Prior Art F is essentially a multistage source-grounded charging/discharging circuit comprising a load capacitor and a MOS transistor.

Other MOS power applications previously filed by the applicant
The first stage source grounded circuit of the on-reset circuit consists of a source grounded MoS transistor which is a driving element and its load resistance.

The above MOS transistor is an enhancement type,
Furthermore, its gate and drain are connected. Similarly, the second stage common source circuit is of the driving source common type M.
It consists of an O8 transistor and its load resistance. The MOS transistor of the first stage common source circuit is of a conductivity type opposite to that of the MOS transistor of the second stage common source circuit. Furthermore, the output voltage of the second stage common source circuit is outputted via a binary circuit and becomes an output control voltage.

From the above explanation, the MOS power-on reset circuit proposed by the applicant is essentially a multi-stage common source circuit comprising a load resistor and a MOS transistor, and is hereinafter abbreviated as a resistive load type power-on reset circuit. Ru.

Further, the MO8 power-on reset circuit including the capacitive load element is hereinafter abbreviated as a capacitive power-on reset circuit.

[Problem to be Solved by the Invention J] Since the output voltage rise characteristic of the above-mentioned rotor load type MOS power-on reset circuit depends on the CR time constant,
When the power supply voltage rises slowly, there is a risk that the IJ @ signal will be output before the power supply voltage is established.

The above problem can be prevented by increasing C and R. However, integrating large C and R inside the rc is not easy and results in a considerable increase in cost.

The method of externally attaching C and R also causes a considerable increase in mounting volume and cost.

Also, in some applications, it is necessary to generate a control signal from the power-on reset circuit to enable the circuit to output as soon as the power supply voltage is established quickly. However, the rise characteristic of the output voltage of the 11fl capacity power-on reset circuit is always constant.

Conversely, since the resistive load type MOS power-on reset circuit described above does not use a capacitor, the II wll voltage input to the binary circuit of the above-mentioned MOS power-on reset circuit sufficiently follows the rapid rise characteristics of the power supply voltage. can. Therefore, as soon as the power supply voltage exceeds a predetermined critical voltage, the circuit can be reset to an output ready state. The problem with this resistive load type MOS power-on reset circuit is that it consumes a lot of power.

Therefore, the object of the present invention is to improve the above-mentioned problems.

One of the objects of the present invention is to develop a MOS power-on system that can handle both rapid and slow rises in the power supply voltage.
The goal is to develop a reset circuit. Another object of the present invention is to develop a low cost MOS power-on reset circuit that can be incorporated into an MO8 integrated circuit.

Means and Effects for Solving Problem E 1 The basic configuration of the present invention is: In a MOS power-on reset circuit having a common source circuit including an enhancement type MOS transistor, a resistive load element and an enhancement type MOS transistor are connected to each other. and a capacitive load type common source circuit stage including a capacitive load and an enhancement type Mos transistor.
This is an OS power-on reset circuit.

The MOS power-on reset circuit of the present invention includes a resistive load type common source circuit and a capacitive load type common source circuit. Therefore, the output voltage delay effect of both can be utilized. That is, a specific feature of the present invention is that the resistive load type source grounded circuit stage and the capacitive load type source grounded circuit stage explained above are connected in multi-stage cascade.

In this way, a MOS power-on reset circuit that is less likely to malfunction even if the power supply voltage rises quickly, and can respond more quickly than a conventional integral type power-on reset circuit when the power supply voltage rises quickly. can be configured.

That is, the resistive load type MOS power-on circuit explained above
The drawbacks of the reset circuit and capacitive load type MOS power-on reset circuit can be improved.

[Example] FIG. 1 is an equivalent circuit diagram representing one embodiment of the present invention.

The first-stage source common circuit 51 consists of a PMOS transistor 1 which is a driving element and its load resistor 6.

The source of the PMOS transistor 1 is connected to the first power supply terminal Vdd, and the drain is connected to the second power supply terminal Vdd through a resistor 6.
[Connected to source end Vss. Further, the gate and drain are connected.

The second stage common source circuit 52 is composed of an NMOS transistor 3 and its load resistor 7. The source of the NMOS transistor 3 is connected to the second power supply terminal VSS, and the drain is connected to the first power supply terminal Vdd via a resistor 7.

The third stage source common circuit 53 is PMO8l-transistor 2
and a capacitor 8 as its load element. The PMO3tMOS transistor is connected to the first power source terminal Vdd, and its drain and the second ffi source terminal VSS are connected via a capacitor g8.

The output contact a of the first stage common source circuit 51 is connected to the gate of the driving transistor 3 of the second stage common source circuit 52. Further, the output contact of the second stage common source circuit 52 is connected to the gate of the driving transistor 2 of the third stage common source circuit 53.

Furthermore, the output contact C of the third stage common source circuit 53 is connected to the input terminal of the Schmitt trigger 5.

The driving transistors 1, 3, and 2 in each stage are of the enhancement type and have a threshold voltage. By connecting the drain and gate of transistor 1, the voltage at the drain is fed back to the gate. As a result, the rise of the output contact voltage of the source grounded circuit 51 is delayed compared to the rise of the power supply voltage Vdd.

Also, since the transistor 1 is of the enhancement type, its output contact a starts to rise in voltage after the power supply voltage exceeds the threshold voltage.

Similarly, the driving transistor 3 of the second stage common source circuit 52 starts conducting after the output voltage of the first stage common source circuit 51 exceeds the threshold voltage of the transistor 3. Therefore, at the output contact of the second stage common source circuit 52, the rise is delayed by the threshold voltage of transistors 1 and 3.

The third stage common source circuit 53 is an integrating circuit having the capacitor 8 as a load. Transistor 2 starts conducting after the voltage at the output contact of the second stage common source circuit falls below Vdd-IVtl.

The channel current of transistor 2 causes capacitor 8 to
is charged. Therefore, the rise of the output voltage at the output contact C of the third stage common source circuit 53 is caused by the rise of the output voltage of the transistor 1.3.
It is delayed by the sum of the delays of the respective threshold voltages and the time constant of the integrating circuit made up of the transistor 2 and the capacitor 8.

The output voltage VC of the third stage common source circuit 53 is input to the Schmitt trigger 5 and converted into binary information with hysteresis. Note that here, instead of the Schmitt trigger 5, it is also possible to use a binary circuit such as a CMOS inverter or a comparator.

The operation of the above circuit will be explained below. Note that the absolute values of the threshold voltages of each MOS transistor 1.2.3 are equal;
It is assumed that the voltage is 1Vtl, and the low potential power supply Vss is Ov. It is assumed that the resistors 6 and 7 are sufficiently large.

1! Under the condition that the Ill voltage Vdd rises, the first
The output voltage Va of the stage source common circuit 51 is: Va=Vss
−0[V] (Vdd<lVt1: Trl 0FF) Also, Va″rVdd−I Vt 1 (Vdd>1Vtl; Trl ON). Therefore, b
The potential vb at the point is vb≠Vdd (Vdd<21Vtl: Tr3 OFF>, and Vb"=7Vss-0[V]'(Vdd>21Vtl; Tr3 ON).

Therefore, the potential Vc at point C is Vc-Vss-0[V] (Vdd<21Vtl:Tr2 OFF>. Therefore, at this time Vo-0[V] (Vo is the output voltage of the Schmitt trigger 5), that is, vo is low level.

Further, when vdd rises and becomes Vdd>21 Vtl, Tr2 is turned on and capacitor 8 is charged.

As a result of this charging, when Vc becomes VC>Vp (Vp is the input voltage of Schmitt trigger 5 when the output voltage of Schmitt 1 - trigger 5 changes to H level), VO is inverted to high level.

Thereafter, VC reaches Vdd, and the output voltage 0 of the Schmitt trigger 5 maintains the "high" level.

Let RO be the conduction resistance of the transistor 2, and CO be the capacitance of the capacitor 8. RO is a function of the channel resistance determined from the well-known saturation and desaturation current equations for PMOS transistors.

FIG. 2 is a voltage waveform diagram when the power supply voltage changes slowly, and FIG. 3 is a voltage waveform diagram when the power supply voltage rises rapidly.

When Vdd reaches 21Vtlkm, take m as To, , Vc
Let T1 be the time when the value reaches vp.

T1 can be expressed by the following formula.

TI -To-Co -Ro -I n (1
-Vp/Vdd) In reality, when the power supply voltage rises rapidly, TO can be almost ignored. That is, as shown in FIGS. 2 and 3, the output voltage Vc of the common source circuit 53 is Vdd=2.
After exceeding 1Vtl, start raising the ground.

Therefore, even if the rise characteristics of the power supply voltage are different, the output voltage VO of the Schmitt trigger 5 is at least equal to the time TO
1 It can be seen that the "low" level can actually be maintained during T1.

As a result, after the necessary and sufficient Vdd is established, the output signal voltage 0 is inverted, and the capacitance of the capacitor 8 can be reduced in size by the output type B delay caused by the common source circuits 51 and 52.

When Vdd<2 l Vt l, transistor 2
is cut off and charging to capacitor 8 is stopped, but Vc remains at V
Since the state of dd is maintained, it is opened at a predetermined time and Vo is maintained at a "high" level.

When the power supply voltage Vdd does not fall below 21Vtl and rises again, the output voltage Vo continues to maintain the high level. Even if there is an instantaneous power supply voltage fluctuation, VO can stably maintain a high level.

FIG. 4 shows an example of changing the potential of output contact a.

In this case, a PMOS transistor 1' having the same structure as the MOS transistor 1 is added between the drain of the MoS transistor 1 and the output contact 8. In this case, the number of PMO8 transistors can be increased by two, three, etc. as necessary. It is also possible to change the ON1m starting voltage of the transistor by inputting the gate voltage of the PMOS transistor by another method such as resistance division.

Note that the resistor 6.7 can be replaced with various load MoS transistors.

In FIG. 5, a MOS transistor 3' having the same structure as the MOS transistor 3 is added between the output contact with the MOS transistor 3 of the first-stage source-grounded circuit in FIG. 1, and the same argument as in FIG. 4 holds true.

FIG. 6 shows an example in which the connection positions of the PMOS transistor 1 and the NMO3 transistor 3 are changed.

Since the logic is reversed, an inverter 50 is added to match the logic.

It is also possible to omit the inverter 50.

[Effects] As described below, the power-on reset circuit of the present invention has two types of circuit formats, and although the resistance value and capacitance are small, it is not affected by the rise characteristics of the power supply voltage.
A reset signal can be generated reliably. Further, by setting a large charging time constant, malfunctions due to instantaneous power supply voltage fluctuations can be prevented.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of one embodiment of the MOS power-on reset circuit of the present invention. 2 and 3 are rising waveform diagrams of the power-on reset circuit of FIG. 1. FIG. 4 is an equivalent circuit diagram of a modified embodiment of the first stage common source circuit shown in FIG. FIG. 5 is an equivalent circuit diagram of a modified embodiment of the second stage common source circuit shown in FIG. FIG. 6 is an equivalent circuit diagram of a modified embodiment of the MOS power-on reset circuit of FIG. 6...Load resistance 7...Load resistance 8...Load capacitor. 51...First stage source grounding circuit 52...Second stage source grounding circuit 53...Third stage source grounding circuit Patent applicant Nippondenso Co., Ltd. z1 Agent Patent attorney Hirodo Okawa Patent attorney Akio Maruyama 51-- -Isso Yabu M Kanden 4 Goro Sauce 8-cho Nanakuchi-ro 5
2----Bo 2 father resistance negative, setting surface a source ↑ side especially seven to 5
3----The 3rd role of the spear, the tributary propagator, the wisdom and epidemic circuit, Figure 2, Figure 3

Claims (1)

[Claims] A MOS power-on reset circuit having a common source circuit stage including an enhancement type MOS transistor, comprising: a resistive load type common source circuit stage including a resistive load element and an enhancement type MOS transistor; 1. A MOS power-on reset circuit comprising: a capacitive load type common source circuit stage comprising a load element and an enhancement type MOS transistor.