JPS63233429A - Additional processor control system - Google Patents

Abstract

PURPOSE:To allow a master processor to transfer operands in parallel with the arithmetic processing of an additional processor by providing the additional processor with many operand buffers to use the buffers for the transfer and operation of operands. CONSTITUTION:An operand buffer group 22 consisting of plural operand buffers stores operands and a command register 23 stores pointer information specifying a command and one operand buffer 22-1 out of plural operand buffers 22-1-22-n. A computing element 21 executes operation by using the operand stored in the operand buffer 22-1 specified by the pointer information stored in the command register 23 on the basis of the command stored in the register 23. An identification register 11 stores the pointer information specifying one operand buffer 22-1 in the operand buffer group 22. The computing element 21 executes operation on the basis of the pointer information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an attached processor control scheme, and more particularly to an operand transfer control scheme from a main processor to an attached processor.

(Prior Art) Conventionally, in this type of attached processor control system, the attached processor is provided with only one operand buffer, which is used by the main processor for the next instruction while the attached processor is processing the previous instruction. When an operand is transferred to an attached processor, the operand used in the previous instruction stored in the operand buffer may be rewritten and a normal operation result may not be obtained.Therefore, the main processor transfers the operand stored in the operand buffer to the previous instruction. It was necessary to wait for the next instruction's operand transfer process at the time when the instruction's arithmetic processing was completed.

[Problem that the invention seeks to solve]

In the conventional attached processor control method described above, the attached processor is not provided with one operand buffer, and the main processor transfers the operands of the next instruction until the attached processor completes the arithmetic processing of the previous instruction. Since a wait has to be made, operand transfer processing in the main processor and arithmetic processing in the additional processor cannot be performed in parallel, resulting in a disadvantage that the processing speed of the information processing system is reduced.

An object of the present invention is to build on the above points and provide a plurality of operand buffers in an additional processor, thereby eliminating the waiting time for operand transfer in the main processor and speeding up the processing of an information processing system. The purpose of the present invention is to provide an additional processor control method that allows the user to control the added processor.

[Means for solving problems]

In the additional processor control method of the present invention, in an information processing system in which a main processor and an additional processor are connected via an address bus, a data bus, and a control signal bus, the additional processor has a plurality of operand buffers that store operands. , a command register storing pointer information indicating a command and one operand buffer of the plurality of operand buffers;
an arithmetic unit that performs an operation based on the command stored in the command register using an operand stored in an operand buffer 1 indicated by pointer information stored in the command register, the main processor comprising:
It includes an identification register that stores pointer information pointing to one of the plurality of operand buffers.

[Effect]

In the attached processor control method of the present invention, a plurality of operand buffers store operands, a command register stores a command and pointer information indicating one of the plurality of operand buffers, and an arithmetic unit stores operands. Based on the command stored in the register, an operation is performed using the operand stored in the operand buffer indicated by the pointer information stored in the command register, and the identification register selects one of the multiple operand buffers. Stores pointer information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an information processing system to which an additional processor control method according to an embodiment of the present invention is applied. This information processing system includes a main processor 1 and an additional processor 2 connected via an address bus 100°, a data bus 101, and a control signal bus 102.

The attached processor 2 has n (positive integer) operand buffers 22, 22-2, . . . that store operands.
, 22-n, and the operand buffers 22, . . . , 22-n of the command and operand buffer group 22. 22-2. ..., 22-n, a command register 23 that stores information (hereinafter referred to as pointer information) i (i is a positive integer of 1: Si≦n), and a command It is configured to include an operand buffer 22 indicated by the pointer information li stored in the command register 23 based on the command stored in the register 23, and an arithmetic unit 21 that performs calculations using the operands stored in the command register 23. .

The main processor 1 has n operand buffers 22, . 22-
2. . . , 22-n. Note that the identification register 11 has n operand buffers 722, , 2
In order to identify 2-2, -, 22-n, the bit width is configured to satisfy at least the relationship 25≧n.

Ru.

Next, the operation of the additional processor control system of this embodiment configured as described above will be explained.

When attempting to perform an operation using the additional processor 2, the main processor 1 uses the pointer information stored in the identification register 11! li i is output to a part of the address bus 100, an operand is output to the data bus 101, and a signal instructing writing is output to the control signal bus 102. As a result, in the additional processor 2, one of the operand buffers 722-i of the operand buffer group 22 is designated, and the operand is written into this operand buffer 22.

Next, the main processor 1 outputs the address specifying the command register 23 to the address bus 100, and sends the command instructing the operation to be executed by the additional processor 2 and the pointer information IIi stored in the identification register 11 to the data. A signal instructing writing is output to the control signal bus 102. As a result, the command and pointer information i are written into the command register 23 in the additional processor 2.

Subsequently, the attached processor 2 is instructed as to the type of operation and the operand buffer 22 to be used by the command and pointer information j stored in the command register 23, so the attached processor 2 performs the specified operation using the specified operand buffer 22.
The operation is executed by the arithmetic unit 21 using the operands stored in the node 22.

Note that at this time, other operand buffers 22, . ....

22- (i,), 22- (i+1),...
It goes without saying that 22-n is not used.

When the transfer of the command and pointer information i to the additional processor 2 is completed, the main processor 1 transfers the identification register 11
The pointer information i stored in
1). Note that this addition is performed as an addition modulo n, and when (i+1) becomes n or more, it cyclically returns to 1.

When transferring operands to be used in the next instruction to attached processor 2, raw processor 1 transfers the identification register 1
The pointer 1n information (i+1) stored in the operand buffer group 2 is output to a part of the address bus 100.
2' specifies the next operand buffer 22-(i+1). Therefore, even if the /iI arithmetic processing using the previously transferred operand is being executed in the additional processor 2, the previously designated operand in the operand buffer 22 will not be rewritten. Therefore, the main processor l does not need to wait for the transfer of the operands to be used in the next /iI calculation to the additional processor 2.

In this way, in the additional processor control system of this embodiment, the operand buffer 22 designated by the main processor 1 for operand transfer is
operand parameters, F22, . 22-2. ..., 2
Since the number changes cyclically between 2 and n, there is no fear that rewriting the operand will interfere with the arithmetic processing of the previous instruction and the arithmetic processing of the next instruction.

〔Effect of the invention〕

As explained above, the present invention provides a plurality of operand buffers in the additional processor, and designates one of the plurality of operand buffers from the main processor and uses it for operand transfer and calculation. is now able to perform operand transfer processing in parallel with the arithmetic processing in the attached processor, eliminating the need for the main processor to wait until the operation processing of the previous instruction is completed before transferring the operand to the attached processor. This has the effect of speeding up the processing of the information processing system.

[Brief explanation of drawings]

The figure is a block diagram showing an information processing system to which an additional processor control method according to an embodiment of the present invention is applied. In the figure, 1... Main processor, 2... Additional processor, 11... Identification register, 21... Arithmetic unit, 22... Operand buffer group, 22, to 22-n... Operand buffer , 23...
・Command register, 100: address bus, 101: data bus, 102: control signal bus.

Claims (1)

[Scope of Claim] An information processing system in which a main processor and an additional processor are connected via an address bus, a data bus, and a control signal bus, wherein the additional processor has a plurality of operand buffers that store operands, commands and a command register that stores pointer information that points to one of the plurality of operand buffers; and a command register that stores pointer information that points to one of the plurality of operand buffers; and a command register that stores pointer information that points to one of the plurality of operand buffers; and a command register that stores pointer information that points to one of the plurality of operand buffers; an arithmetic unit that performs an operation using stored operands, and the main processor includes an identification register that stores pointer information indicating one of the plurality of operand buffers. Additional processor control method.