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JPS63229852A - semiconductor equipment - Google Patents

semiconductor equipment

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Publication number
JPS63229852A
JPS63229852A JP6470487A JP6470487A JPS63229852A JP S63229852 A JPS63229852 A JP S63229852A JP 6470487 A JP6470487 A JP 6470487A JP 6470487 A JP6470487 A JP 6470487A JP S63229852 A JPS63229852 A JP S63229852A
Authority
JP
Japan
Prior art keywords
layer
electrode wiring
tin
poly
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6470487A
Other languages
Japanese (ja)
Inventor
Yasunari Abe
泰成 安部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6470487A priority Critical patent/JPS63229852A/en
Publication of JPS63229852A publication Critical patent/JPS63229852A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の電極配線に、第1層にポリシリコンを、第
2層のバリア層に窒化チタン(TiN)とTi或いはT
iNとTiシリサイドを、第3層にアルミニウムを使用
することにより、コンタクト抵抗の低い、導電性のよい
、断線の少ない電極配線を得ることが出来る。
[Detailed Description of the Invention] [Summary] For the electrode wiring of a semiconductor device, polysilicon is used as the first layer and titanium nitride (TiN) and Ti or T are used as the second barrier layer.
By using iN and Ti silicide and aluminum for the third layer, electrode wiring with low contact resistance, good conductivity, and less disconnection can be obtained.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の電極配線構造に係わり、特に断線
の少ない、導電性のよい3層構造の電極配線に関する。
The present invention relates to an electrode wiring structure for a semiconductor device, and more particularly to an electrode wiring having a three-layer structure with good conductivity and less disconnection.

半導体装置の電極配線には、はじめアルミニウム(AI
)が多く使用されたが、AI単層ではストレスマイグレ
ーションあるいはエレクトロマイグレーションで断線し
易い。このため、A1の下に不純物含有ポリシリコン(
ポリSi)を敷いて、AIを切れ難く或いはAIが切れ
てもポリStで温通が保てるようにしたものがあるが、
これもA1とポリStが同和反応をおこしピントが発生
ずる欠点がある。
Aluminum (AI) was first used for electrode wiring of semiconductor devices.
) were often used, but single-layer AI is prone to disconnection due to stress migration or electromigration. Therefore, the impurity-containing polysilicon (
There are some that are laid with poly-Si) to make it difficult to break the AI, or even if the AI breaks, the poly-St can be used to maintain heat.
This also has the disadvantage that A1 and polySt cause a dosing reaction, resulting in out-of-focus.

本発明は、この飼−ポリSi両層の間に中間層としてT
iN とT473、或いはTiN含有Tiシリサイドを
形成し、導電性のよい断線のない電極配線を得ようとす
るものである。
In the present invention, T is used as an intermediate layer between both the feed and poly-Si layers.
The purpose is to form iN and T473 or TiN-containing Ti silicide to obtain electrode wiring with good conductivity and no disconnection.

〔従来の技術〕[Conventional technology]

第2図は従来例における電極配線構造を説明するための
断面模式図である。
FIG. 2 is a schematic cross-sectional view for explaining an electrode wiring structure in a conventional example.

この図において、1はSi基板、2はその表面層に形成
した例えばN型の拡散領域である。
In this figure, 1 is a Si substrate, and 2 is, for example, an N-type diffusion region formed in its surface layer.

このSi基板1の表面に5iOz膜等の絶縁膜3が形成
され、これにコンタクト孔が窓開けされた後、不純物を
ドープしたポリSi4がCVD法で被着され、ついでこ
の上にA16がスパッタリング法で被覆される。ついで
、A16およびポリSL4をパターニングして電極配線
層を形成する。
An insulating film 3 such as a 5iOz film is formed on the surface of this Si substrate 1, and after a contact hole is opened in this, poly-Si4 doped with impurities is deposited by the CVD method, and then A16 is sputtered onto this. Covered by law. Next, A16 and poly SL4 are patterned to form an electrode wiring layer.

このようにして形成したAI−ポリStの電極配線はA
I単層のものに比してストレスマイグレーション、エレ
クトロマイグレーションによる断線は可成り低減するこ
とが出来るも、電極形成後の熱処理によりAI−ポリS
i間に固相反応を起こし、AI中にStが固溶し、ピッ
トが発生する欠陥を有する。
The AI-polySt electrode wiring formed in this way is A
Although the disconnection due to stress migration and electromigration can be considerably reduced compared to the single layer I layer, the heat treatment after electrode formation
It has a defect in which a solid phase reaction occurs between the i and St dissolves in solid solution in the AI, resulting in the generation of pits.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

Δl−ポリSi間の固相反応を防止し、且つ導電性良好
な電極配線をうる。
Solid phase reaction between Δl and poly-Si can be prevented and electrode wiring with good conductivity can be obtained.

〔問題点を解決するための手段〕 上記問題点の解決は、 シリコン基板の表面より導出された電極配線層が第1層
が不純物を含存するポリシリコンでなり、第2層がチタ
ンと窒化チタン、またはチタンシリサイドと窒化チタン
でなり、第3層がアルミニウムよりなるものを有してい
る本発明による半導体装置により達成される。
[Means for solving the problem] The solution to the above problem is that the first layer of the electrode wiring layer led out from the surface of the silicon substrate is polysilicon containing impurities, and the second layer is made of titanium and titanium nitride. or titanium silicide and titanium nitride, and the third layer is aluminum.

〔作用〕[Effect]

電極配線の^l−ポリSt間にバリア層としてTiNを
もつ層を入れる。即ち、TiN ffjの下にTi層を
敷くか、又は、TiNとTiNシリサイド(TtSix
)の混合層とすれば、コンタクト抵抗の低い、且つAl
−ポリSt間反応の少ない3層構造の電極配線を得るこ
とが出来る。
A layer containing TiN is inserted as a barrier layer between the electrode wiring ^l and polySt. That is, a Ti layer is placed under the TiN ffj, or TiN and TiN silicide (TtSix
), it has low contact resistance and Al
- It is possible to obtain an electrode wiring having a three-layer structure with less reaction between poly-St.

〔実施例〕〔Example〕

第1図(a) 、(b)は本発明における電極配線構造
を説明するための断面模式図である。
FIGS. 1(a) and 1(b) are schematic cross-sectional views for explaining the electrode wiring structure in the present invention.

第1図(a)は実施例(1)で、酎−ポリSi間のバリ
ア層として、TiN 1gとTilを用いたものである
FIG. 1(a) shows Example (1), in which 1 g of TiN and Til were used as a barrier layer between the aluminum and poly-Si.

1はSi基板で、この表面層に、例えばN型の拡散領域
2が形成されている。
Reference numeral 1 denotes a Si substrate, and an N-type diffusion region 2, for example, is formed in the surface layer of the Si substrate.

このSi基板1の表面に5iO1膜或いはPSG(Ph
ospho−5ilicate Glass )等の絶
縁膜3を形成し、これにコンタクト孔を窓開けした後、
不純物をドープしたポリSiの第17!!4をCVD法
で約1000〜2000人波着する。ついで、この上に
第2層の下側層としてTi5−1をスパッタリング法で
約200大破着する。
A 5iO1 film or PSG (Ph
After forming an insulating film 3 such as ospho-5ilicate glass and opening a contact hole in it,
No. 17 of poly-Si doped with impurities! ! Approximately 1,000 to 2,000 people will arrive using the CVD method. Next, approximately 200 layers of Ti5-1 are deposited on this layer by sputtering as a lower layer of the second layer.

更に、この上に第2層の上側層としてTiN5−2の層
をスパッタリング法で約1500人形成する。このスパ
ッタリングはTiNの電極でAr中で行うか、Ti電極
でAr+N、  雰囲気でリアクティブスパッタリ、ン
グ法によって行う。
Furthermore, about 1,500 TiN5-2 layers are formed on this layer by sputtering as an upper layer of the second layer. This sputtering is performed using a TiN electrode in Ar, or using a Ti electrode in an Ar+N atmosphere using a reactive sputtering method.

第3層としてのA16を厚さ約1μm、スパッタリング
で被着する。ついで、異方性ドライエツチングにより電
極配線バターニングを行う。
A third layer of A16 is applied to a thickness of approximately 1 μm by sputtering. Next, electrode wiring patterning is performed by anisotropic dry etching.

これにより、TIの導電性の良さとTiNのバリア性の
良さを備えた中間層である第2層を形成することが出来
る。
As a result, it is possible to form a second layer which is an intermediate layer having the good conductivity of TI and the good barrier properties of TiN.

第1図(b)は実施例(2)で、AI−ポリSi間のバ
リア層として、TiNとTiSi、の混合層を用いたも
のである。
FIG. 1(b) shows Example (2), in which a mixed layer of TiN and TiSi was used as a barrier layer between AI and poly-Si.

この図において、1はSi基板で、この表面層に、例え
ばN型の拡散領域2が形成されている。
In this figure, 1 is a Si substrate, and an N-type diffusion region 2, for example, is formed in the surface layer of the Si substrate.

このSi基板1の表面、にSiO□膜或いはPSG等の
絶縁膜3を形成し、これにコンタクト孔を窓開けした後
、不純物をドープしたポリSiの第1層4をCVD法で
約1000〜2000人波着する。ついで、この上に第
2層として、Tiをスパッタリング法で約1000大破
着する。
After forming an insulating film 3 such as SiO□ film or PSG on the surface of this Si substrate 1 and opening a contact hole in this, a first layer 4 of poly-Si doped with impurities is deposited by CVD to a thickness of about 1000~ 2,000 people arrive. Then, as a second layer, about 1000 Ti is deposited on top of this by sputtering.

ついで、これを950℃の窒素雰囲気中でアニールする
ことにより、シリサイド化とナイトライド化を同時に行
う。即ち、TiとポリSi4との界面からは漸次TiS
i、が形成され、またTiの表面からは窒素の拡散によ
り表面程TiNに富んだ第2層5が形成される。
Then, by annealing this in a nitrogen atmosphere at 950° C., silicidation and nitridation are simultaneously performed. That is, TiS gradually forms from the interface between Ti and poly-Si4.
i, is formed, and a second layer 5 rich in TiN is formed from the surface of Ti due to the diffusion of nitrogen.

これにより、バリア層の第2層11は TiSix+T
iNで構成され、TiSi、は導電性に富み、TiNの
窒素はSiがTiSi、中に入るのを阻止するので、A
IとSiの相互反応が起こらず、断線が防止され、コン
タクト抵抗も充分低い電極配線を得ることが出来る。
As a result, the second layer 11 of the barrier layer is TiSix+T
Composed of iN, TiSi is highly conductive, and nitrogen in TiN prevents Si from entering TiSi.
No interaction between I and Si occurs, wire breakage is prevented, and electrode wiring with sufficiently low contact resistance can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、半導体装
置の電極配線に、第1層にポリSiを、第2層のバリア
層にTiN 、l!:Ti或いはTiNとTtStXを
、第3層に酎を使用することにより、ポリSiとAIの
反応を阻止することが出来、コンタクト抵抗の低い、導
電性のよい、断線の少ない電極配線を得ることが出来る
As described above in detail, according to the present invention, the electrode wiring of a semiconductor device includes poly-Si as the first layer, TiN as the second barrier layer, and l! : By using Ti or TiN and TtStX for the third layer, it is possible to prevent the reaction between poly-Si and AI, and to obtain electrode wiring with low contact resistance, good conductivity, and less disconnection. I can do it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a) 、(b)は本発明における電極配線構造
を説明するための断面模式図、 第2図は従来例における電極配線構造を説明するための
断面模式図である。 この図において、 1はSi基板、 2は拡散領域、 3は絶縁膜(Sift膜)、 4は第1層(ポリSi)、 5は第2N。 5−1は第2層(Ti)、 5−2は第2層(TiN )、 6は第3層(A1)
FIGS. 1(a) and 1(b) are schematic cross-sectional views for explaining an electrode wiring structure in the present invention, and FIG. 2 is a schematic cross-sectional view for explaining an electrode wiring structure in a conventional example. In this figure, 1 is a Si substrate, 2 is a diffusion region, 3 is an insulating film (Sift film), 4 is a first layer (poly-Si), and 5 is a second N layer. 5-1 is the second layer (Ti), 5-2 is the second layer (TiN), 6 is the third layer (A1)

Claims (1)

【特許請求の範囲】 シリコン基板(1)の表面より導出された電極配線層が
第1層(4)が不純物を含有するポリシリコンでなり、 第2層(5)がチタンと窒化チタン、またはチタンシリ
サイドと窒化チタンでなり、 第3層がアルミニウム(6)よりなるものを有している ことを特徴とする半導体装置。
[Claims] In the electrode wiring layer led out from the surface of the silicon substrate (1), the first layer (4) is made of polysilicon containing impurities, and the second layer (5) is made of titanium, titanium nitride, or A semiconductor device comprising titanium silicide and titanium nitride, and a third layer comprising aluminum (6).
JP6470487A 1987-03-19 1987-03-19 semiconductor equipment Pending JPS63229852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6470487A JPS63229852A (en) 1987-03-19 1987-03-19 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6470487A JPS63229852A (en) 1987-03-19 1987-03-19 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS63229852A true JPS63229852A (en) 1988-09-26

Family

ID=13265798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6470487A Pending JPS63229852A (en) 1987-03-19 1987-03-19 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS63229852A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63280440A (en) * 1987-05-12 1988-11-17 Toshiba Corp Semiconductor device and manufacture thereof
US5313100A (en) * 1991-04-26 1994-05-17 Mitsubishi Denki Kabushiki Kaisha Multilayer interconnection structure for a semiconductor device
KR100458465B1 (en) * 1997-12-30 2005-04-06 주식회사 하이닉스반도체 Bit line formation method of semiconductor device
KR100509221B1 (en) * 1997-03-31 2005-12-09 세이코 엡슨 가부시키가이샤 Display
JP2014225692A (en) * 2008-12-25 2014-12-04 ローム株式会社 Semiconductor device and method of manufacturing semiconductor device
JP2014241426A (en) * 2008-12-25 2014-12-25 ローム株式会社 Semiconductor device
CN104900705A (en) * 2008-12-25 2015-09-09 罗姆股份有限公司 Semiconductor device
US9219127B2 (en) 2009-12-24 2015-12-22 Rohm Co., Ltd. SiC field effect transistor
US9406757B2 (en) 2008-12-25 2016-08-02 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63280440A (en) * 1987-05-12 1988-11-17 Toshiba Corp Semiconductor device and manufacture thereof
US5712140A (en) * 1991-04-19 1998-01-27 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing interconnection structure of a semiconductor device
US5313100A (en) * 1991-04-26 1994-05-17 Mitsubishi Denki Kabushiki Kaisha Multilayer interconnection structure for a semiconductor device
US5475267A (en) * 1991-04-26 1995-12-12 Mitsubishi Denki Kabushiki Kaisha Multilayer interconnection structure for a semiconductor device
KR100509221B1 (en) * 1997-03-31 2005-12-09 세이코 엡슨 가부시키가이샤 Display
KR100458465B1 (en) * 1997-12-30 2005-04-06 주식회사 하이닉스반도체 Bit line formation method of semiconductor device
US9293575B2 (en) 2008-12-25 2016-03-22 Rohm Co., Ltd. Semiconductor device
US9837531B2 (en) 2008-12-25 2017-12-05 Rohm Co., Ltd. Semiconductor device
CN104900705A (en) * 2008-12-25 2015-09-09 罗姆股份有限公司 Semiconductor device
US12199178B2 (en) 2008-12-25 2025-01-14 Rohm Co., Ltd. Semiconductor device
JP2014225692A (en) * 2008-12-25 2014-12-04 ローム株式会社 Semiconductor device and method of manufacturing semiconductor device
US9406757B2 (en) 2008-12-25 2016-08-02 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
JP2016154236A (en) * 2008-12-25 2016-08-25 ローム株式会社 Semiconductor device
JP2014241426A (en) * 2008-12-25 2014-12-25 ローム株式会社 Semiconductor device
US10693001B2 (en) 2008-12-25 2020-06-23 Rohm Co., Ltd. Semiconductor device
USRE48072E1 (en) 2008-12-25 2020-06-30 Rohm Co., Ltd. Semiconductor device
USRE48289E1 (en) 2008-12-25 2020-10-27 Rohm Co., Ltd. Semiconductor device
US11152501B2 (en) 2008-12-25 2021-10-19 Rohm Co., Ltd. Semiconductor device
US11804545B2 (en) 2008-12-25 2023-10-31 Rohm Co., Ltd. Semiconductor device
US9219127B2 (en) 2009-12-24 2015-12-22 Rohm Co., Ltd. SiC field effect transistor

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