JPS63229726A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS63229726A JPS63229726A JP6462087A JP6462087A JPS63229726A JP S63229726 A JPS63229726 A JP S63229726A JP 6462087 A JP6462087 A JP 6462087A JP 6462087 A JP6462087 A JP 6462087A JP S63229726 A JPS63229726 A JP S63229726A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide resin
- ceramics substrate
- mum
- mos
- memory element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000919 ceramic Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 229920001721 polyimide Polymers 0.000 claims abstract description 9
- 239000009719 polyimide resin Substances 0.000 claims abstract description 9
- 229910000679 solder Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000002285 radioactive effect Effects 0.000 abstract description 4
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 abstract description 2
- 229910052776 Thorium Inorganic materials 0.000 abstract description 2
- 229910052770 Uranium Inorganic materials 0.000 abstract description 2
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 abstract description 2
- 230000005260 alpha ray Effects 0.000 abstract 1
- 239000010409 thin film Substances 0.000 description 11
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特にＭＯＳ形半導体
記憶素子を搭載部品とする混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device having a MOS type semiconductor memory element as a mounted component.
近年、混成集積回路装置の高機能化が進むにっれて、搭
載部品の高密度化が図られている。従来、半導体素子を
高密度実装した混成集積回路装置として知られるものは
半田バンプを形成した半導体素子を、配線導体層が形成
されたセラミック基板上にリフロー・ソルダリングによ
り接続した所謂フリップ・チップ技術による構造のもの
である。In recent years, as hybrid integrated circuit devices have become more sophisticated, the density of mounted components has been increased. Conventionally, what is known as a hybrid integrated circuit device in which semiconductor elements are mounted in high density is the so-called flip-chip technology, in which a semiconductor element on which solder bumps are formed is connected by reflow soldering to a ceramic substrate on which a wiring conductor layer is formed. It has a structure according to
この従来の混成集積回路装置は、半導体素子の動作領域
とセラミック基板とが互いに対向する構造となっている
ので、半導体素子がＭＯＳ型半導体記憶素子（以下ＭＯ
Ｓメモリ素子という）である場合であると、セラミック
基板材料中に不純物として存在するウラニウム（Ｕ）ま
たはトリウム（Ｔｈ）から放射されるα線によって、Ｍ
ＯＳメモリ素子の記憶内容が反転する通常ソフト・エラ
ーと呼ばれる誤動作が生じ易くなる。一般に、ＭＯＳメ
モリ素子のソフト・エラー防止策として知られる方法は
、ＭＯＳメモリ素子上に厚さ３０μｍ以上のポリミィド
ド樹脂層を形成してα線を遮へいすることである。しか
しながら、このような厚い樹脂層を形成した半導体素子
に微小な半田バンプを形成することは困難であるので混
成集積回路装置に簡単には適用することができない。This conventional hybrid integrated circuit device has a structure in which the operating area of the semiconductor element and the ceramic substrate face each other, so that the semiconductor element is a MOS type semiconductor memory element (hereinafter referred to as MOSFET).
In the case of an S memory element), the M
Malfunctions, usually called soft errors, in which the storage contents of the OS memory element are reversed, are likely to occur. Generally, a known method for preventing soft errors in MOS memory devices is to form a polyimide resin layer with a thickness of 30 μm or more on the MOS memory device to shield α rays. However, since it is difficult to form minute solder bumps on a semiconductor element formed with such a thick resin layer, it cannot be easily applied to a hybrid integrated circuit device.
本発明の目的は、上記の状況に鑑み、セラミック基板中
に存在する放射性不純物によるソフト・エラーの発生を
有効に防止し得る構造を備えた混成集積回路装置を提供
することである。In view of the above circumstances, an object of the present invention is to provide a hybrid integrated circuit device having a structure that can effectively prevent the occurrence of soft errors due to radioactive impurities present in a ceramic substrate.
本発明によれば混成集積回路装置は、配線導体を有する
セラミック基板と、前記配線導体のバンブ電極との接触
面を除く領域を埋める膜厚３０μｍ以上のボリミイド樹
脂層と、半田バンプを介し前記配線導体と電気接続され
る半導体チップとを含む。According to the present invention, a hybrid integrated circuit device includes a ceramic substrate having a wiring conductor, a borimide resin layer having a thickness of 30 μm or more that fills a region other than a contact surface of the wiring conductor with a bump electrode, and a borimide resin layer having a thickness of 30 μm or more and connecting the wiring through solder bumps. It includes a semiconductor chip that is electrically connected to a conductor.
すなわち、本発明によればα線の遮へいに有効なポリミ
ィドド樹脂層は３０ｔｔｍ以上の膜厚でセラミック基板
側に形成される。このことによりセラミック基板中に存
在する放射性不純物が放射するα線はセラミック基板上
で阻止されるので対向配置されたＭＯＳメモリ素子を侵
かすことばない。That is, according to the present invention, a polyimide resin layer effective in shielding alpha rays is formed on the ceramic substrate side with a film thickness of 30 ttm or more. As a result, alpha rays emitted by radioactive impurities present in the ceramic substrate are blocked on the ceramic substrate, so that they do not attack the MOS memory element disposed opposite to each other.
〔実施例〕 以下図面を参照して本発明の詳細な説明する。〔Example〕 The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示す断面図である０本実施
例によれば、混成集積回路装置は、積層セラミック基板
１と、この積層セラミック基板とにバターニング形成さ
れた１０００人。FIG. 1 is a sectional view showing one embodiment of the present invention. According to this embodiment, a hybrid integrated circuit device includes a multilayer ceramic substrate 1 and a multilayer ceramic substrate formed by patterning on the multilayer ceramic substrate.
１０００人および６０００人の各膜厚のニクロム（Ｎｉ
Ｃｒ）パラジウム（Ｐｄ）および金（Ａｕ）の３層蒸着
膜からなる導体薄膜配線２と、スクリーン印刷法により
、上記薄膜配線導体のバンブ電極との接触面を除く領域
を埋めるように塗布され、まず８０℃３０分のキュア処
理とつづく３５０℃までの連続昇温と３５０°Ｃ３０分
のキュア処理とによって形成された厚さ４５μｍのポリ
ミィドド樹脂層３と、鉛（Ｐｂ）−錫（Ｓｎ）合金から
なる半田バンプ４を介し導体薄膜配線２と積層セラミッ
ク基板１上でリフロー・ソルダリング法により接続され
るＭＯＳメモリ素子５とを含む。本実施例によれば、積
層セラミック基板１に含まれたウラニウム（Ｕ）または
トリウム（Ｔｈ）などが放射するα線はＭＯＳメモリ素
子５に到達する前にボリミイド樹脂層３で大きく阻止さ
れるのでＭＯＳメモリ素子５にソフト・エラーを生じせ
しめることはない。Nichrome (Ni) film thickness of 1000 and 6000
Cr) A conductor thin film wiring 2 consisting of a three-layer vapor deposited film of palladium (Pd) and gold (Au), which is coated by screen printing method so as to fill the area excluding the contact surface of the thin film wiring conductor with the bump electrode, First, a 45 μm thick polyimide resin layer 3 formed by curing at 80°C for 30 minutes, followed by continuous temperature rise to 350°C and curing at 350°C for 30 minutes, and a lead (Pb)-tin (Sn) alloy. A MOS memory element 5 is connected on a multilayer ceramic substrate 1 to a conductor thin film wiring 2 via solder bumps 4 made up of the following. According to this embodiment, alpha rays emitted by uranium (U) or thorium (Th) contained in the multilayer ceramic substrate 1 are largely blocked by the borimid resin layer 3 before reaching the MOS memory element 5. No soft errors will occur in the MOS memory element 5.
第２図は本発明の他の実施例を示す断面図である。本実
施例によれば混成集積回路装置は、アルミナ・セラミッ
ク基板６と、このアルミナ・セラミック基板６上にパタ
ーニング形成された厚さ１０００人の窒化タンタル（Ｔ
ａ２Ｎ）スパッタ薄膜および厚さ８０００人の金属真空
蒸着薄膜の２ＪＩ構造からなり３５０℃１時間の抵抗安
定化熱処理を終えた薄膜抵抗体７と、この上面に積層形
成された前実施例と同じ３Ｎ蒸着膜から成る薄膜配線導
体２と、スピンコード法を用いて基板全面に塗布され１
５０℃３０分キュア処理とつづく３００℃までの連続昇
温と３００℃１時間のキュア処理および酸素スパッタエ
ツチングとによってバンブ電極との接触面間を埋めるよ
うに形成された膜厚的４５μｍのポリミィドド樹脂層３
と、鉛（ｐｂ）−錫（Ｓｎ）合金からなる半田バンプ４
を介し薄膜配線導体２とアルミナ・セラミック基板６上
でリフローソルダリング法により接続されるＭＯＳメモ
リ素子５とを含む。FIG. 2 is a sectional view showing another embodiment of the present invention. According to this embodiment, the hybrid integrated circuit device includes an alumina ceramic substrate 6 and a tantalum nitride (T
a2N) Thin film resistor 7, which has a 2JI structure of a sputtered thin film and a metal vacuum evaporated thin film with a thickness of 8000 mm and has been heat treated for resistance stabilization at 350°C for 1 hour, and the same 3N resistor as in the previous example laminated on its upper surface. A thin film wiring conductor 2 made of a vapor-deposited film and a thin film wiring conductor 1 coated on the entire surface of the substrate using a spin code method.
A 45 μm thick polyamide resin film was formed by curing at 50°C for 30 minutes, followed by continuous heating to 300°C, curing at 300°C for 1 hour, and oxygen sputter etching to fill the space between the contact surfaces with the bump electrodes. layer 3
and solder bumps 4 made of lead (pb)-tin (Sn) alloy.
It includes a MOS memory element 5 which is connected via a thin film wiring conductor 2 and an alumina ceramic substrate 6 by a reflow soldering method.
本実施例におけるボリミイド樹脂層３は前実施例と全く
同様にアルミナ・セラミック基板６からのα線を基板上
で有効に阻止する作用・効果を奏するのでＭＯＳモリ素
子５にソフト・エラーが発生されることはない。The bolimide resin layer 3 in this embodiment has the function and effect of effectively blocking α rays from the alumina ceramic substrate 6 on the substrate, just as in the previous embodiment, so that no soft error occurs in the MOS memory element 5. It never happens.
以上詳細に説明したように、本発明によれば厚さ３０μ
ｍ以上のポリミィドド樹脂層がセラミック基板上に形成
されセラミック基板の材料内に存在する放射性不純物が
放射するα線からＭＯＳメモリ素子を保護し得る構造を
備えるので、所謂ソフト・エラーと呼ばれる記憶内容の
反転現象の発生を予防することができる。すなわち、高
密度実装の混成集積による半導体記憶装置の実現に顕著
なる効果を奏し得る。As explained in detail above, according to the present invention, the thickness is 30 μm.
A polyimide resin layer of m or more is formed on the ceramic substrate and has a structure capable of protecting the MOS memory element from alpha rays emitted by radioactive impurities present in the material of the ceramic substrate. The occurrence of the reversal phenomenon can be prevented. That is, a remarkable effect can be achieved in realizing a semiconductor memory device by hybrid integration with high density packaging.
第１図は本発明の一実施例を示す断面図、第２図は本発
明の他の実施例を示す断面図である。
１・・・積層セラミック基板、２・・・薄膜配線導体、
３・・・ポリミィドド樹脂層、４・・・半田バンプ、５
・・・Ｍ ＯＳメモリ、６・・・アルミナセラミック基
板、７・・・薄膜抵抗体。FIG. 1 is a sectional view showing one embodiment of the invention, and FIG. 2 is a sectional view showing another embodiment of the invention. 1... Laminated ceramic substrate, 2... Thin film wiring conductor,
3...Polymerized resin layer, 4...Solder bump, 5
...MOS memory, 6...Alumina ceramic substrate, 7...Thin film resistor.
Claims (1)
バンブ電極との接触面を除く領域を埋める膜厚３０μｍ
以上のポリミィド樹脂層と、半田バンプを介し前記配線
導体と電気接続される半導体チップとを備えることを特
徴とする混成集積回路装置。A film thickness of 30 μm that fills the area excluding the contact surface between the ceramic substrate having the wiring conductor and the bump electrode of the wiring conductor.
A hybrid integrated circuit device comprising the above polyimide resin layer and a semiconductor chip electrically connected to the wiring conductor via solder bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6462087A JPS63229726A (en) | 1987-03-18 | 1987-03-18 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6462087A JPS63229726A (en) | 1987-03-18 | 1987-03-18 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63229726A true JPS63229726A (en) | 1988-09-26 |
Family
ID=13263483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6462087A Pending JPS63229726A (en) | 1987-03-18 | 1987-03-18 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63229726A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2650121A1 (en) * | 1989-07-21 | 1991-01-25 | Nec Corp | Electronic chip support |
| US5264726A (en) * | 1989-07-21 | 1993-11-23 | Nec Corporation | Chip-carrier |
| WO1994008442A1 (en) * | 1992-10-02 | 1994-04-14 | Irvine Sensors Corporation | Fabrication of dense parallel solder bump connections |
| US6459125B2 (en) | 1998-02-26 | 2002-10-01 | Mitsubishi Denki Kabushiki Kaisha | SOI based transistor inside an insulation layer with conductive bump on the insulation layer |
| US10964632B2 (en) | 2019-03-20 | 2021-03-30 | Toshiba Memory Corporation | Semiconductor device |
-
1987
- 1987-03-18 JP JP6462087A patent/JPS63229726A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2650121A1 (en) * | 1989-07-21 | 1991-01-25 | Nec Corp | Electronic chip support |
| US5264726A (en) * | 1989-07-21 | 1993-11-23 | Nec Corporation | Chip-carrier |
| WO1994008442A1 (en) * | 1992-10-02 | 1994-04-14 | Irvine Sensors Corporation | Fabrication of dense parallel solder bump connections |
| US6459125B2 (en) | 1998-02-26 | 2002-10-01 | Mitsubishi Denki Kabushiki Kaisha | SOI based transistor inside an insulation layer with conductive bump on the insulation layer |
| US10964632B2 (en) | 2019-03-20 | 2021-03-30 | Toshiba Memory Corporation | Semiconductor device |
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