JPS63229511A - semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a structure for transferring data using an internal data bus in a semiconductor integrated circuit such as a microprocessor.

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit that processes data having a data width of 8 bits, 16 bits, 32 bits, etc., a data bus with the number of pits corresponding to the data width is provided internally. As shown in Figure 2, signals are transmitted via this data bus through multiple internal output ports (26, etc.).
and an input port (27, etc.). The output from a certain output is connected to the data bus (22° to 2
2n). The input port 27 receives the synchronization signal 21
When ="1", input from data buses 220 to 22fi is accepted. The data buses 220 to 22n are normally precharged by the precharge circuit 211 during a period when no signals are transmitted (synchronization signal 21="0"). ,
When the discharged state is set to 22fi='ゞpresent'), and the synchronizing signal 21=°゛1''', the data bus 22n=+ is set to no 1 only when the expected signal is ''present'.
1, 1? As shown in FIG. 3, during the period when the synchronization signal 21="1", the data bus 2
2Q, including enough time to sufficiently discharge the data bus 22. The potential drops to around Ov. Synchronous signal Z-
During the period of N o ++, the data bus 220 is set to the power supply voltage (vDD, vDD=5v) by the precharge circuit 211.
) will be precharged to around 5v.

Problems to be Solved by the Invention As described above, in the conventional example, the data buses 22Q to 22fi
is charged and discharged from OV to around 6V according to signal exchange. Data bus 220-22
Since n is connected to many input/output ports, it has a large load capacitance co-Cn, which slows signal transmission and requires sufficient time for sufficient discharge. is restricted.

Furthermore, since a large load capacitance Co--Cn is charged and discharged, the power supply current increases due to this charging and discharging.

An object of the present invention is to provide a data bus 2 involved in signal transmission.
This provides a method of minimizing the charge and discharge of 20 to 22n necessary for signal transmission, thereby improving response speed and reducing current consumption.

Means to Solve the Problem The present invention provides a data bus consisting of a plurality of bits with a sense line having the same configuration as one bit of the data bus, and connects a sense circuit for determining the presence or absence of a signal to the sense line. An output port drive signal that controls the output from the output port and port to the data bus is simultaneously applied to the sense output circuit for the sense line, and when the sense circuit detects the signal,
By stopping the output port drive signal mentioned above, holding the signal from the data bus at the input port at that point, and starting precharging to the data bus and sense line, the signal to the data bus is The purpose is to minimize the necessary and minimum amount of communication. Furthermore, when the sense circuit no longer detects a signal due to precharging, precharging is stopped, thereby shortening the time required for precharging.

According to the present invention, the transmission of a signal to a data bus is replaced with the transmission of a signal to a sense line having the same configuration as the data bus, and is detected by a sense circuit. By driving the output port circuit only during the period necessary for signal transmission, unnecessary discharge of the data bus is suppressed, and as a result, it is possible to return to a state with no signal (precharge state) in a short time. can.

Embodiment FIG. 1 shows an embodiment of the present invention. In this figure, an example using an n-channel MOS transistor will be explained. 11 is a synchronization signal. When data 160 to 16n are selected from the output port 16 (only one is shown in this example, but usually multiple ports are required) by the output port control signal 13, the output port drive signal 13D selects the data 160 to 16n.
Data 16Q~16fi Data bus 12Q~12n
Output to.

At this time, the output port drive signal 13 is also applied to the sense line 12S.
D, the sen east output circuit 16S (always sense line 12
Input 1eSG is connected to vno to discharge S. ) to discharge the sense line 12g.

Input port 17 (only one is shown in this example,
Usually multiple pieces are required. ) is the input port control signal 14
input port drive signal 14D when selected by
data 16 from data buses 120-12n
Q~16fi is transmitted to internal inputs 170~17fi,
At the time when the input port drive signal 14D changes from "pa1" to "o", the internal human powers 17Q to 17n are latched (held).1
S is a dummy load connected to the sense line. Capacity C1a -01n of data bus 120 to 12n under equal constraints
The dummy 17s may be omitted if the sense line capacitance C1S can be realized to have the same value as one bit (the sum of the capacitance of the input/output port and the parasitic capacitance of the wiring). The precharge circuit 111 is composed of a constant voltage circuit section and a precharge section. The constant voltage circuit section has a gate and a drain connected to a power supply (VDD) of a transistor 12QP with a relatively small gm, and a source connected to a data bus 120 to 12.
fi and applies a holding voltage that is lower than the power supply voltage VDD by a threshold voltage vT. 120D is a very small gm transistor, which connects the data bus 12Q to 1271.
prevent the voltage from becoming too high in steady state. 11
0F, data buses 120 to 12n transmit signals,
This transistor is used for rapid charging when the voltage becomes lower than the holding voltage, and is controlled by the precharge drive signal 11D. In this case as well, the transistor 11P is connected in series to the charging transistor 110P so that the voltage approaches the holding voltage by charging. The precharge circuit 118 for the sense line 12S also has the same configuration.

Sense line M1s detects the potential level of sense line 12S. The output of the sense circuit 18 is '○'' in the precharged state (at the holding voltage), and the output port drive signal 1
3D is discharged within 1″ period and +10
+l−I+ 1″′.

The judgment output 151 of the sense circuit 18 is used as the output of the OR circuit 162 and deactivates the output port drive signal 13D. The delay circuit 191 deactivates the output port drive signal 13D during the period of the synchronization signal 11, so that the sense circuit 18
The period for judgment will be extended. The output of the sense circuit 18 is '
1", the output and the output passed through the delay circuit 192 are applied to the OR circuit 154, and the output 153 of the OR circuit 154 causes the precharge drive signal 11D to charge the data buses 12Q to 12n and the sense line 12S. When the potential of the sense line 12S becomes high due to charging (when the output of the sense circuit 18 changes from "1" to "o"), charging is continued for the period of the delay circuit 192, and then,
Stop charging. The decision threshold voltage of the sense circuit 18 is made to be the same as that of each input port 16. Also, this threshold voltage is the data bus 120
12n and the sense line 12S are precharged (holding voltage), it is sufficient that the voltage is less than or equal to the voltage that guarantees the minimum noise margin.

Next, the circuit operation will be explained according to FIG. The output port drive signal 13D is synchronized with the rise of the synchronization signal 11.
(The phase difference between the synchronization signal 11 and the output port drive signal 13D takes into account the delay caused by the circuit. In the following explanation, FIG. 4 is written taking into account the delay as well.)

When the data 160 is 11'', the data bus 12Q is discharged, and when it becomes lower than the threshold voltage of the sense circuit 18, the judgment output 161 becomes °°0'', and -
Based on the determination output 161, the output port drive signal 13
D is stopped. Similarly, the input port drive signal 14D rises in synchronization with the rise of the synchronization signal 11, and transmits the signal of the data bus 12Q to the internal input 170. Judgment output 1
When 51 becomes 10'', the input port drive signal 14D is also stopped and the internal power 17Q is latched.Data 16o
When the bit signal of the data bus 12o is 0'', the sense circuit 18 of the bit of the data bus 12o does not operate. Therefore, if the signals of all the bits are ``no'', the judgment output 161 cannot be obtained, and in FIG.
It will look like the dotted line. In the precharge section, when the sense circuit 18 detects that the voltage of the sense line 125 becomes equal to or lower than the threshold voltage, the precharge drive signal 11D is activated.
When the sense circuit 18 detects a voltage equal to or higher than the threshold voltage, it is deactivated after an appropriate delay time.

Effects of the Invention As described above, according to the present invention, it is only necessary to discharge the potential of the data bus until the sense circuit can judge the signal. It can be done in a limited time. At this time,
The data bus signals are transmitted to the necessary input ports at about the same time that the sense circuit determines the signals. or,
Since the data path is not discharged unnecessarily, the time for precharging can be shortened, and the overall circuit operation can be speeded up. Furthermore, the precharge has a precharge section that charges quickly and a constant potential (holding voltage).
It consists of a constant voltage circuit section and rapidly performs only the minimum necessary precharge period. Therefore, since charging and discharging of the data bus can be limited to a minimum potential difference, an increase in power supply current accompanying this charging and discharging can be minimized.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional example, and Fig. 3 explains operating waveforms and timing of main parts of the conventional circuit. FIG. 4 is a timing diagram illustrating the operation waveforms and timing of the main parts of an embodiment of the present invention. 11...Synchronization signal, 12Q~12n...
・Data bus, 12S...Sense line, 13...
...Output port control signal, 14...Input port control signal, 16...Output port, 16S...
...Sense output circuit, 1T...Input port, 17S...Dummy, 151...Judgment output, 191...Delay circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure Theta Nomas 15/fi 3 Doka Figure 2 Cheetah Bus

Claims (2)

[Claims] (1) In a system that controls the transfer of signals to a data bus connected to a plurality of internal input/output ports using a synchronization signal, a sense line is provided in parallel with the data bus,
A sense line output circuit driven by a respective output port drive signal that drives each output port is connected to the sense line, a sense circuit is provided for detecting a voltage level of the sense line, and the sense circuit a circuit that inactivates the output port drive signal by detecting the output from the line output circuit; a control circuit that holds data of the input port by the output detection; and a control circuit that inactivates the output port drive signal at least. 1. A semiconductor integrated circuit comprising: a constant voltage circuit that brings the voltages of the data bus and the sense line close to a constant value. (2) The constant voltage circuit is configured in parallel with a circuit that starts charging following output detection and stops charging when the output detection ends, and a circuit that charges to a constant voltage. A semiconductor integrated circuit according to claim 1, characterized in that: