JPS63228337A - Method for driving parity generation circuit - Google Patents

Abstract

PURPOSE:To enhance the speed-up of a parity generation circuit by keeping first and second signal lines in an electric potential by which respective transistors can be made in non-connected state at a holding time and keeping only either of the signal lines in the electric potential by which the transistors can be made in the connected state at an operating time. CONSTITUTION:All the input data pairs Do and the inverse of Do, Di and the inverse of Di and Dn and the inverse of Dn are kept in the low electric potential by which the transistor in the parity generation circuit is not connected at the holding time. Therefore, at the holding time a current path between a power source VCC and a ground does not exist. In the operating state, since either of input data pair in the low electric potential is driven in order to be in the high electric potential, the transistor connected to an input data line which becomes in the high electric potential becomes in the connected state. The input data pair Do and the inverse of Do close to the power source VCC are inputted in the parity generation circuit at first and the input data pair Dn and the inverse of Dn farthest from the power source VCC are finally inputted. Thus, the parity can be generated at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for driving a parity generation circuit, and more particularly to a method for driving a high-speed parity generation circuit suitable for an error correction circuit incorporated in a semiconductor memory device.

(Prior art) In recent years, in semiconductor memory devices, alpha particle resistance 2
From the viewpoint of improving yield, a method of mounting an error self-correction circuit on a chip is attracting attention. In the method of mounting an error self-correction circuit on-chip, it is required that the delay time due to the error self-correction circuit be as short as possible. Most of the time required for error correction is spent on parity generation.
It is strongly desired to increase the speed of this parity generation circuit.

This is the third known high-speed parity generation circuit.
There is one shown in the figure. This parity generation circuit is an IEE
Eji~Naru Saibu Solid State Circuits (I
EEE Journal of 5solid 5tat
eCircuits) Volume 5C-20, No. 5, 95
From page 8 to page 963 “A 7O-ns Wor
d-Wide 1-Mbit ROM With 0n-
Chip Error Correction C1r
This was shown in a paper titled ``Cuits''.

In Figure 3, DO and Do, ・-, Dn & Dn
The data pairs are complementary to each other, and during standby, all data pairs are kept at a high potential, and the potential of the node inside the parity generation circuit becomes the ground potential. In operation, one of each data pair is at a low potential, forming a bus within the parity generation circuit. The input of the NAND gate 39 is the slowest data pair among the data pairs, and after the bus is formed in the parity generation circuit, the output of the NAND gate becomes a high potential, and the output of the NAND gate connects the bus in the parity generation circuit. It will spread. Therefore, after the NAND gate is activated,
The time it takes to obtain parity is determined by the propagation delay time during which the signal propagates within the parity generation circuit.

(Problem to be solved by the invention) In the conventionally known parity generation circuit described above, the NAND
Since the slowest data pair is used as the signal to activate the gate, the time from when the earliest data pair arrives at the parity generation circuit to when parity is output is as long as the earliest data pair reaches the parity generation circuit. The time from arrival until the latest data pair arrives at the parity generation circuit, and the NAND game! The output of . is the sum of the propagation delay time of propagation through the parity generation circuit. FIG. 4 shows this situation. In FIG. 4, data pair D
o, Do are the earliest signals and the data pair Di, Di
represents the slowest signal. data pair [)i,
The change in Di activates the NAND gate, and the NAND
The output of the gate is propagated within the parity generation circuit and output. Therefore, in such conventional technology, the time from the first change in the data pair until the output is obtained is the sum of the data pair delay time and the propagation delay time within the parity generation circuit.
It cannot be lower than that. That is, since the propagation delay time within the parity generation circuit is fully reflected, there is a problem that as the number of input data pairs of the parity generation circuit increases and the signal propagation path becomes longer, the time required to obtain a parity output becomes longer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method that can improve the above-mentioned problems of the prior art and drive a parity generation circuit faster than the prior art.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides means in which the first signal line is the gate electrode, the first node is the drain electrode, and the 20th node is the drain electrode. a first transistor serving as a source electrode; and the first signal line serving as a gate electrode;
a second transistor having a third node as a do/in electrode, a fourth node as a source electrode, a second signal line as a gate electrode, and the first node as a drain electrode;
a third transistor having the fourth node as a source electrode; and a fourth transistor having the second signal line as a gate electrode, the i-th node as a drain electrode, and the second node as a source electrode. In the method for driving a parity generation circuit in which logic blocks consisting of transistors are connected in multiple stages, the first and second signal lines are kept at a potential that allows each of the transistors to become non-conductive during standby, and the first and a second signal line, only one of the signal lines is set to a potential that can make the transistor conductive.

(Function) The present invention has improved the problems in the prior art by employing the above-described driving method. In other words, in the conventional technology, all input data pairs are kept at a high potential during standby, and all nodes inside the parity generation circuit are electrically connected to the ground, so one of the input data pairs is at a low level. It was necessary to propagate the logic "1" signal after the state inside the parity generation circuit was determined and the output signal of the NAND gate (logic "1" signal) was not shorted to ground. In the present invention, all input data pairs are kept at a low potential during standby and one of them is set at a high potential when activated, so there is no steady path to ground as in the prior art, and therefore propagation is possible. A high potential state (logic "1" signal) can be applied before the internal state of the parity generation circuit is determined, increasing speed.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a method of driving the parity generation circuit shown in FIG. 2 as a typical embodiment of the present invention. Second
The parity generation circuit shown in the figure is similar to the conventional parity generation circuit shown in FIG. Although the only difference is the 1D generation circuit and the signal source that propagates a high potential, the driving method of the present invention makes it possible to use a signal source that propagates XmVcc as shown in FIG. Now, in the driving method of the present invention, as shown in FIG. 1, during standby, all input data pairs are kept at a low potential that does not cause the transistors connected to DO to conduct. Therefore, in the standby state, there is no current path between the power supply Vcc shown in FIG. 2 and the ground. In the operating state, as shown in Figure 1, one of the input data pairs that is at a low potential is driven to a high potential, so that it is connected to the input data line that is at a high potential. The transistor becomes conductive. In this embodiment, as shown in FIG. 1, input data pairs Do and Do that are closest to the power supply Vcc are input to the parity generation circuit in order, and finally, the input data pairs closest to the power supply Vcc are input to the parity generation circuit.
An input data pair Dn, Dn separated from is input.

First, consider the case where the input data pair Do, Do is input to the parity generation circuit. Assume that Do now changes to a high potential, and at this time transistors 3 and 4 of block A become conductive. Therefore, the power supply Vcc is propagated to the lower output line of block A via transistor 3, and the ground potential is propagated to the upper output line of block A via transistor 4. These become the outputs of block A and are output from block A with a slight delay after the input data pair DO2Do is input. Thereafter, the voltage @1Vcc and the ground potential propagate as the input data lines are sequentially input, and when the i-th input data pair Di, Di is input, it is output from the i-th block B with a little delay, and the last input data pair is output from the i-th block B. When Dn and Dn are input, an output is output from the last block C, and the output of the parity generation circuit is obtained.

As is clear from the above explanation, in the driving method of the present invention, each time one of the input data pairs becomes a high potential, outputs are sequentially output from the corresponding blocks, so that the last input data pair Dn,
When Dn is input, the output of the entire parity generation circuit is obtained. Therefore, as can be seen by comparing FIG. 1 and FIG. 4, in the present invention, only one block is required to be activated after the last input data pair is input, so in the prior art, it was necessary to activate all blocks. Significant speedup is achieved compared to . Moreover, it is easy to understand that in the present invention, the higher the number of inputs to the parity generation circuit, that is, the number of blocks, the faster the processing speed can be achieved compared to the prior art.

(Effects of the Invention) As described above, according to the present invention, there is provided a method for driving a parity generation circuit that can generate parity faster as the number of inputs increases compared to conventional methods for driving a parity generation circuit.

[Brief explanation of drawings]

FIG. 1 is a timing diagram showing a driving method according to a typical embodiment of the present invention, and FIG. 2 is a diagram showing a parity generation circuit to which the driving method of FIG. 1 is applied. Further, FIG. 3 is a diagram showing the configuration of a conventional parity generation circuit, and the fourth section is a timing diagram showing its driving method. 1-12.31-38...transistor, 39...
NAND gate, A, B, C, D, E...block.

Claims (1)

[Scope of Claims] A first transistor having a first signal line as a gate electrode, a first node as a drain electrode, and a second node as a source electrode; and the first signal line as a gate electrode. , a second node with a third node as a drain electrode and a fourth node as a source electrode.
a third transistor having a second signal line as a gate electrode, the first node as a drain electrode, and the fourth node as a source electrode; and a third transistor as the second signal line as a gate electrode. , a method for driving a parity generation circuit in which a logic block including a fourth transistor having the third node as a drain electrode and the second node as a source electrode is connected in multiple stages, wherein the first and the fourth transistors are connected in a standby state. The second signal line is maintained at a potential that allows each of the transistors to be rendered non-conductive, and during operation, only one of the first and second signal lines is maintained at a potential that enables the transistor to be rendered conductive. A method for driving a parity generation circuit, characterized in that: