JPS63226981A - Superconducting integrated circuit device and its manufacturing method - Google Patents
Superconducting integrated circuit device and its manufacturing methodInfo
- Publication number
- JPS63226981A JPS63226981A JP62060441A JP6044187A JPS63226981A JP S63226981 A JPS63226981 A JP S63226981A JP 62060441 A JP62060441 A JP 62060441A JP 6044187 A JP6044187 A JP 6044187A JP S63226981 A JPS63226981 A JP S63226981A
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- Prior art keywords
- film
- integrated circuit
- circuit device
- sputtering
- manufacturing
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
本発明の超伝導１１植回路装置のキャパシタは、Ｎｂ膜
（下部電圧） ／ Ｎｂ２０５ｇ （誘電体ｊ！Ｉ）
／Ａ立ＩＩ！Ｉ！（上部電極）の構造をしている。[Detailed Description of the Invention] [Summary] The capacitor of the superconducting 11-plant circuit device of the present invention has a Nb film (lower voltage) / Nb205g (dielectric j!I).
/A standing II! I! (upper electrode) structure.
このため、配線膜としてのＮｂ１ｌをスパッタ法により
形成する場合にも、Ｎｂ２Ｏ５ＩＩはＡｌ膜によりカバ
ーされているので損傷を受けない、従って特性の良好な
キャパシタを得ることができる。またＮｂ膜をスパッタ
法により形成できるので、超伝導臨界温度の低下を招か
ない高品質の超伝導膜を得ることができる。Therefore, even when Nb1l is formed as a wiring film by sputtering, Nb2O5II is not damaged because it is covered by the Al film, so a capacitor with good characteristics can be obtained. Furthermore, since the Nb film can be formed by sputtering, a high-quality superconducting film that does not cause a drop in the superconducting critical temperature can be obtained.
本発明は超伝導集積回路装置およびその製造方法に関す
るもであり、更に詳しく言えば超伝導集積回路装置のキ
ャパシタの製造とその製造方法に関するものである。The present invention relates to a superconducting integrated circuit device and a method of manufacturing the same, and more particularly, to a capacitor of a superconducting integrated circuit device and a method of manufacturing the same.
第３図は従来例に係る超伝導集積回路装置に用いるキャ
パシタの断面図であり、Ｎｂ［（下部電極） １／ Ｎ
ｂ２Ｏ５膜（誘１！膜）２／Ｎｂ膜（上部電極）４の構
造となっている。あるいは上部電極としてはＰｂ −Ｉ
ｎ−Ａｕ膜又はＰｂＭが用いられている（第４６回応用
物理学会予稿集
Ｐ３８８ 、（１９８５）） 。FIG. 3 is a cross-sectional view of a capacitor used in a conventional superconducting integrated circuit device, in which Nb[(lower electrode) 1/N
It has a structure of b2O5 film (dielectric film) 2/Nb film (upper electrode) 4. Or as the upper electrode, Pb-I
An n-Au film or PbM is used (Proceedings of the 46th Japan Society of Applied Physics P388, (1985)).
ところで高品質のＮｂ膜を得るためには、該Ｗｂ＠をス
パッタ法により形成することが望ましい、しかしスパッ
タ法で１部電極としてのＮｂ１ｌを形成する場合には、
スパッタ中に下地のＮｂ２Ｏ５膜が破壊されて誘電体と
しての性質が劣化するという問題がある。By the way, in order to obtain a high-quality Nb film, it is desirable to form the Wb@ by a sputtering method. However, when forming Nb1l as a partial electrode by a sputtering method,
There is a problem in that the underlying Nb2O5 film is destroyed during sputtering and its dielectric properties deteriorate.
ｔたＥ、Ｂ（エレクトロン・ビーム）蒸着法により上部
電極としてのＮｂ！Ｉを形成する場合は、下地のＮｂｚ
Ｏｓ膜に損傷を与えないが、Ｗｂ膜自体の膜厚が悪くな
り、例えば超伝導臨界温度（Ｔｃ）が下がるという問題
がある。（なおＮｂ膜は融点が高いので、抵抗加熱蒸着
法では形成できない、）
なお上部電極として、Ｎｂ１Ｊの代わりにＰｂ −Ｉｎ
−Ａｕ ＷＪあるいはＰｂ膜を用いて上部電極を形成
する構成もあるが、かかる膜は融点が低いので、超伝導
集積回路装置の製造中に発生する熱や、製造後、絶対零
度付近で使用する際の熱サイクルに耐えることができず
、実質的に使用不可１蔚であるという問題がある。Nb as the upper electrode by E,B (electron beam) evaporation method. When forming I, the base Nbz
Although this does not damage the Os film, there is a problem that the thickness of the Wb film itself deteriorates, and for example, the superconducting critical temperature (Tc) decreases. (Note that the Nb film has a high melting point, so it cannot be formed by resistance heating evaporation.) As the upper electrode, Pb -In was used instead of Nb1J.
- There is also a configuration in which the upper electrode is formed using an Au WJ or Pb film, but since such a film has a low melting point, it is difficult to handle the heat generated during the manufacturing of superconducting integrated circuit devices or to use it at temperatures near absolute zero after manufacturing. There is a problem in that it is unable to withstand the heat cycles that occur, making it virtually unusable.
本発明はかかる従来の問題に鑑みて創作されたものであ
り、膜質の良好なＮｂ膜を用いて形成可能な超伝導集積
回路装置のキャパシタの構造とその製造方法の提供を目
的とする。The present invention was created in view of such conventional problems, and aims to provide a structure of a capacitor of a superconducting integrated circuit device that can be formed using an Nb film of good film quality, and a method for manufacturing the same.
〔ＦＦ！１８点を解決するための手段〕第１図に本発明
の超伝導集積回路装このキャパシタの原理構成を示す。[FF! Means for Solving the 18 Points] FIG. 1 shows the principle structure of a superconducting integrated circuit device and a capacitor according to the present invention.
すなわち、Ｎｂ ［（下部電極）５の上にＮｂ２０５膜
（誘電体［）６が形成され、更に該ＮｂｚＯｓ膜６の上
にＡｌ膜（上部電極）８が形成されている。そしてその
上にＮｂ膜（配線膜）９が形成された構造となっている
。なお７はＳ ｉＯｚ Ｉｇ！（層間絶縁膜）である。That is, an Nb205 film (dielectric material) 6 is formed on the Nb205 (lower electrode) 5, and an Al film (upper electrode) 8 is further formed on the NbzOs film 6. The structure is such that an Nb film (wiring film) 9 is formed thereon. 7 is S iOz Ig! (interlayer insulating film).
本発明によれば、Ｎｂｚ Ｏ５膜６の上にＡｌ膜８が形
成されている。このためその上にスパッタ法により配線
膜としてのＮｂ ！Ｉ９を形成するとき、Ｎｂ２Ｏ５膜
６はＡｕ膜８によって保護される。すなわちＮｂｚＯｓ
ｌ！Ｊはスパッタによる損傷を受けないのでその誘電体
膜としての性能は線棒される。またＮｂ１ｉ！！（配線
膜）もスパッタ法により形成できるので、高品質のＮｂ
！Ｉを形成することが可能となる。According to the present invention, the Al film 8 is formed on the Nbz O5 film 6. For this reason, Nb! is deposited as a wiring film on top of it by sputtering. When forming I9, the Nb2O5 film 6 is protected by the Au film 8. That is, NbzOs
l! Since J is not damaged by sputtering, its performance as a dielectric film is poor. Nb1i again! ! (wiring film) can also be formed by sputtering, so high-quality Nb
! It becomes possible to form I.
次に図を参照しながら本発明の実施例について説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第２図は本発明の実施例に係る超伝導集積回路装置のキ
ャパシタの製造方法を説明する図である。FIG. 2 is a diagram illustrating a method of manufacturing a capacitor of a superconducting integrated circuit device according to an embodiment of the present invention.
（１）まずＳｉ基板１０ｈにＮｂ膜１１．ＡＭ−Ａ交Ｏ
ｘ １２およびＮｂ［１３を同−真空内で順次、連続成
膜する。このときＮｂｌｇｔはｄＣ又はｒｆマグネトロ
ンスパ７夕で成膜し、Ｎｂ１ｌＱ１１は２００〜３００
ｎｍ、Ｎｂ膜１３は５０膜ｍの膜厚である。またＡｌは
ｄｃ又はｒｆスパッタ法により３〜ｌｏｎｍで成膜し、
その後、酸素を導入してＡ１表面にＡＪＩＯｘを形成す
る。(1) First, the Nb film 11 is placed on the Si substrate 10h. AM-A
x12 and Nb[13 are sequentially formed into films in the same vacuum. At this time, Nblgt was formed into a film using a dC or RF magnetron spa for 7 days, and Nb1lQ11 was formed into a film with a concentration of 200 to 300
The Nb film 13 has a thickness of 50 m. In addition, Al is formed into a film with a thickness of 3 to lonm by DC or RF sputtering method,
Thereafter, oxygen is introduced to form AJIOx on the A1 surface.
なおＳｉ基板ｌＯとＮｂ膜１１との間に、熱酸化膜等が
形成されていてもよい（第２図（ａ））。Note that a thermal oxide film or the like may be formed between the Si substrate IO and the Nb film 11 (FIG. 2(a)).
（２）次いでレジスト膜１４をパターニングした後、該
レジスト膜１４をマスクとしてＮｂ膜１３、Ａ交−Ａ交
Ｏｘ膜１２の加工を行なった後、該レジスト膜内をマス
クとしてＮｂｇｔｉを陽極酸化してＮｂＮｂ２０ｓ１１
５を形成する（第２図（ｂ））。(2) Next, after patterning the resist film 14, using the resist film 14 as a mask, the Nb film 13 and the A-AC Ox film 12 are processed, and then Nbgti is anodized using the inside of the resist film as a mask. NbNb20s11
5 (Fig. 2(b)).
（３）次にレジスト１１１４を除去した後に１１００ｎ
程度のＡｌｌ膜を形成し、更にリフト法又はドライエツ
チング法等によりパターニングしてＡＭ！ｆＩ１７（キ
ャパシタの上部電極）を形成する（同図（ｃ））。(3) Next, after removing the resist 1114,
After forming an All film of about 100 mL, patterning is performed using a lift method or dry etching method to obtain AM! fI17 (upper electrode of the capacitor) is formed (FIG. 3(c)).
（４）次いで層間絶縁膜としてのＳ ｉ０２膜１８を、
スパッタ法あるいはＣＶＤ法により全面に被着する（同
図（ｄ））。(4) Next, the Si02 film 18 as an interlayer insulating film,
It is deposited over the entire surface by sputtering or CVD (FIG. 2(d)).
（５）次に５ｉ０２ｆｉ ｌ ８を部分的にエツチング
することにより上部電極コンタクト用の開口部１９゜２
０を形成する（同図（ｅ））。(5) Next, by partially etching 5i02fil 8, an opening 19°2 for the upper electrode contact is created.
0 is formed ((e) in the same figure).
（８）次にＡｒ （アルゴン）によるスパッタクリー
ニングを行う、これによりＮｂ１１９１３およびＡ！Ｌ
膜１７の表面は清浄になる。このときスパッタによる損
傷を受は易いＮｂｚＯｓＭ １５はＡ１１ｌｌ１７によ
り保護されているので、これらの膜質は劣化しない。(8) Next, perform sputter cleaning with Ar (argon), which results in Nb11913 and A! L
The surface of membrane 17 becomes clean. At this time, since NbzOsM 15, which is easily damaged by sputtering, is protected by A11ll17, the quality of these films does not deteriorate.
次いでスパッタ法によりＮｂ１５ｉを被着した後にバタ
ーニングして配線！！；１２１および２２を形成する（
同図（ｆ））、この場合、Ｗｂ！Ｉ２１゜２２はスパッ
タ法により形成されるので、所定の超伝導臨界温度を有
する高品質のＮｂ膜である。Next, Nb15i was deposited by sputtering, followed by patterning and wiring! ! ; forming 121 and 22 (
(f)), in this case, Wb! Since I21°22 is formed by sputtering, it is a high quality Nb film having a predetermined superconducting critical temperature.
なおＮｂ２Ｏ５膜１５は、それぞれＡ１１７により保護
されているので、このときもＮｂスパッタによる損傷を
受けない。Note that since the Nb2O5 films 15 are each protected by A117, they are not damaged by the Nb sputtering at this time as well.
このようにして、本発明の実施例によれば、高性能のキ
ャパシタと高性能のジョセフソン接合素子を同一基板上
に集結化して製造することが可能となる。In this way, according to embodiments of the present invention, a high performance capacitor and a high performance Josephson junction element can be integrated and manufactured on the same substrate.
なおＡｌ膜は超伝導膜ではないので若干の抵抗値をもつ
が、その膜厚は薄いのでその抵抗値は低い、このため動
作上問題とならない。Note that since the Al film is not a superconducting film, it has a slight resistance value, but since the film thickness is thin, the resistance value is low, and therefore does not pose a problem in operation.
以上説明したように１本発明の製造方法によれば、誘電
体膜としてのＮｂ２Ｏ５膜の上にＡｌ膜が予め形成され
た構造となっている、このため配線膜としてのＮｂ［を
スパッタ法により形成する場合にも、該ＮｂｚＯｓ１ｇ
ｉをスパッタによる損傷から保護することができる。こ
れにより高性能の超伝導キャパシタが得られる。またＮ
ｂ１ｌをスパッタ法により形成することができるので、
高品質のＮｂ膜が得られ、所定の超伝導臨界温度を有す
る高品質の超伝導集積回路装置を製造することが可能と
なる。As explained above, according to the manufacturing method of the present invention, the Al film is pre-formed on the Nb2O5 film as the dielectric film. Also when forming, the NbzOs1g
i can be protected from damage caused by sputtering. This results in a high-performance superconducting capacitor. Also N
Since b1l can be formed by sputtering,
A high-quality Nb film is obtained, and it becomes possible to manufacture a high-quality superconducting integrated circuit device having a predetermined superconducting critical temperature.
第１図は本発明の超伝導集積回路装置のキャパシタの原
理構成を示す断面図。
第２図は本発明の実施例に係る超伝導集結回路装置の製
造方法を説明する図、
第３図は従来例に係る超伝導集積回路装置のキャパシタ
を説明する図である。
（符号の説明）
１．５．１１・・・Ｎｂ膜（下部電極）、２．６．１５
・−＊ｂ２ｏｓｌ！ｇ（、ｄ電体ＷＪ） 。
３．７．１８・・・Ｓ ｉ０２膜（Ｊ！’間絶間膜縁膜
４・・・Ｎｂ１ｌ！！（上部電極）、
８．１７・・・Ａ見膜（上部電極）、
９．２１．２２・・−Ｎｂ膜（配線Ｆ！Ｊ）、１２・−
Ａ ｌ −Ａ見Ｏ！膜。
本し絹へ免理説Ｂη図
叱りぢ多トイタリｄへａａ月ａ
第３図
４にΔσ日月のプＦぶｈ俵Ｆ釦６朗［く第２図（での］
）
吹トイさＥＩＰＩめつＣ方送例°右？、８月トｎ第２図
（び２）FIG. 1 is a sectional view showing the principle structure of a capacitor of a superconducting integrated circuit device according to the present invention. FIG. 2 is a diagram illustrating a method of manufacturing a superconducting integrated circuit device according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a capacitor of a conventional superconducting integrated circuit device. (Explanation of symbols) 1.5.11...Nb film (lower electrode), 2.6.15
・-*b2osl! g(, d electric body WJ). 3.7.18...S i02 film (J!' insulating film edge film 4...Nb1l!! (upper electrode), 8.17...A membrane (upper electrode), 9.21. 22...-Nb film (wiring F!J), 12...-
Al-A look O! film. Honshi silk to the theory Bη diagram scolding data to itari d to aa month a Fig. 3
) Squirting toy sa EIPI Metsu C direction example ° right? , August Figure 2 (bi 2)
Claims (3)
膜）／Ａｌ膜（上部電極）からなるキャパシタを有する
ことを特徴とする超伝導集積回路装置。(1) A superconducting integrated circuit device characterized by having a capacitor consisting of a Nb film (lower electrode)/Nb_2O_5 film (dielectric film)/Al film (upper electrode).
いることを特徴とする特許請求の範囲第１項に記載の超
伝導集積回路装置。(2) The superconducting integrated circuit device according to claim 1, wherein a Nb film (wiring film) is formed on the Al film.
る工程と、 該Ｎｂ膜の上にＮｂ＿２Ｏ＿５膜（誘電体膜）を形成す
る工程と、 該Ｎｂ膜の上にＡｌ膜（上部電極）を形成する工程と、 該Ａｌ膜の上に配線膜としてのＮｂ膜をスパッタ法によ
り形成する工程とを有することを特徴とする超伝導集積
回路装置の製造方法。(3) A step of forming a Nb film (lower electrode) by sputtering, a step of forming an Nb_2O_5 film (dielectric film) on the Nb film, and an Al film (upper electrode) on the Nb film. 1. A method for manufacturing a superconducting integrated circuit device, comprising: forming a Nb film as a wiring film on the Al film by sputtering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62060441A JPS63226981A (en) | 1987-03-16 | 1987-03-16 | Superconducting integrated circuit device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62060441A JPS63226981A (en) | 1987-03-16 | 1987-03-16 | Superconducting integrated circuit device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63226981A true JPS63226981A (en) | 1988-09-21 |
Family
ID=13142361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62060441A Pending JPS63226981A (en) | 1987-03-16 | 1987-03-16 | Superconducting integrated circuit device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63226981A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1267412A3 (en) * | 2001-06-15 | 2006-01-11 | Northrop Grumman Corporation | Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits |
| US7820996B2 (en) * | 2005-01-31 | 2010-10-26 | Samsung Electronics Co., Ltd. | Nonvolatile memory device made of resistance material and method of fabricating the same |
| US8101983B2 (en) | 2003-06-03 | 2012-01-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same |
| US8513634B2 (en) | 2003-12-17 | 2013-08-20 | Samsung Electronics Co., Ltd. | Nonvolatile data storage, semicoductor memory device including nonvolatile data storage and method of forming the same |
| US20200266234A1 (en) * | 2018-04-20 | 2020-08-20 | D-Wave Systems Inc. | Systems and methods for fabrication of superconducting devices |
| US11730066B2 (en) | 2016-05-03 | 2023-08-15 | 1372934 B.C. Ltd. | Systems and methods for superconducting devices used in superconducting circuits and scalable computing |
| US11839164B2 (en) | 2019-08-19 | 2023-12-05 | D-Wave Systems Inc. | Systems and methods for addressing devices in a superconducting circuit |
| US11856871B2 (en) | 2018-11-13 | 2023-12-26 | D-Wave Systems Inc. | Quantum processors |
| US11879950B2 (en) | 2018-05-16 | 2024-01-23 | D-Wave Systems Inc. | Systems and methods for addressing devices in a superconducting circuit |
| US11930721B2 (en) | 2012-03-08 | 2024-03-12 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
| US11957065B2 (en) | 2017-02-01 | 2024-04-09 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
| US12102017B2 (en) | 2019-02-15 | 2024-09-24 | D-Wave Systems Inc. | Kinetic inductance for couplers and compact qubits |
| US12367412B2 (en) | 2020-12-03 | 2025-07-22 | 1372934 B.C. Ltd. | Systems and methods for fabricating flux trap mitigating superconducting integrated circuits |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60787A (en) * | 1983-06-16 | 1985-01-05 | Nippon Telegr & Teleph Corp <Ntt> | Tunnel type josephson junction element and manufacture thereof |
| JPS61181178A (en) * | 1985-02-06 | 1986-08-13 | Rikagaku Kenkyusho | Josephson junction element and manufacture thereof |
-
1987
- 1987-03-16 JP JP62060441A patent/JPS63226981A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60787A (en) * | 1983-06-16 | 1985-01-05 | Nippon Telegr & Teleph Corp <Ntt> | Tunnel type josephson junction element and manufacture thereof |
| JPS61181178A (en) * | 1985-02-06 | 1986-08-13 | Rikagaku Kenkyusho | Josephson junction element and manufacture thereof |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1267412A3 (en) * | 2001-06-15 | 2006-01-11 | Northrop Grumman Corporation | Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits |
| US8101983B2 (en) | 2003-06-03 | 2012-01-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same |
| US8164130B2 (en) | 2003-06-03 | 2012-04-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same |
| US8513634B2 (en) | 2003-12-17 | 2013-08-20 | Samsung Electronics Co., Ltd. | Nonvolatile data storage, semicoductor memory device including nonvolatile data storage and method of forming the same |
| US7820996B2 (en) * | 2005-01-31 | 2010-10-26 | Samsung Electronics Co., Ltd. | Nonvolatile memory device made of resistance material and method of fabricating the same |
| US8168469B2 (en) | 2005-01-31 | 2012-05-01 | Samsung Electronics Co., Ltd. | Nonvolatile memory device made of resistance material and method of fabricating the same |
| US11930721B2 (en) | 2012-03-08 | 2024-03-12 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
| US11730066B2 (en) | 2016-05-03 | 2023-08-15 | 1372934 B.C. Ltd. | Systems and methods for superconducting devices used in superconducting circuits and scalable computing |
| US11957065B2 (en) | 2017-02-01 | 2024-04-09 | 1372934 B.C. Ltd. | Systems and methods for fabrication of superconducting integrated circuits |
| US20200266234A1 (en) * | 2018-04-20 | 2020-08-20 | D-Wave Systems Inc. | Systems and methods for fabrication of superconducting devices |
| US11879950B2 (en) | 2018-05-16 | 2024-01-23 | D-Wave Systems Inc. | Systems and methods for addressing devices in a superconducting circuit |
| US11856871B2 (en) | 2018-11-13 | 2023-12-26 | D-Wave Systems Inc. | Quantum processors |
| US12102017B2 (en) | 2019-02-15 | 2024-09-24 | D-Wave Systems Inc. | Kinetic inductance for couplers and compact qubits |
| US11839164B2 (en) | 2019-08-19 | 2023-12-05 | D-Wave Systems Inc. | Systems and methods for addressing devices in a superconducting circuit |
| US12367412B2 (en) | 2020-12-03 | 2025-07-22 | 1372934 B.C. Ltd. | Systems and methods for fabricating flux trap mitigating superconducting integrated circuits |
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