JPS63224354A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63224354A JPS63224354A JP62058008A JP5800887A JPS63224354A JP S63224354 A JPS63224354 A JP S63224354A JP 62058008 A JP62058008 A JP 62058008A JP 5800887 A JP5800887 A JP 5800887A JP S63224354 A JPS63224354 A JP S63224354A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- semiconductor layer
- high resistance
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 abstract description 9
- 230000005685 electric field effect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 22
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体装置が備える高
抵抗領域の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a high resistance region included in a semiconductor device.
第3図は従来の半導体装置が備える高抵抗領域の断面図
で、高抵抗領域は半導体基板1上にフィールド絶縁膜2
を介して設けられた高抵抗半導体層3から成り金属配線
4a、4bはその両端部からコンタクト孔を介して引出
される。ここで、5は眉間絶縁膜である。FIG. 3 is a cross-sectional view of a high resistance region included in a conventional semiconductor device.
The metal wirings 4a and 4b are formed of a high-resistance semiconductor layer 3 provided through contact holes, and metal wirings 4a and 4b are drawn out from both ends thereof through contact holes. Here, 5 is an insulating film between the eyebrows.
しかしながら、この従来構造によると革抵抗半導体層3
の抵抗率は半導体層自身の膜質のみによって決定され、
半導体基板1の電位はもとより他の部分の電位にも全く
依存しない構成がとられているので所望の抵抗値を得る
ためには半導体層の幅、長さおよび厚さなどを精密に制
御せればならず、特に高抵抗を得ようとすれば大きな面
積を占有せしめなければならない不都合を生じる。However, according to this conventional structure, the resistive semiconductor layer 3
The resistivity of is determined only by the film quality of the semiconductor layer itself,
Since the structure is completely independent of the potential of the semiconductor substrate 1 as well as the potential of other parts, it is necessary to precisely control the width, length, thickness, etc. of the semiconductor layer in order to obtain the desired resistance value. In particular, if high resistance is to be obtained, a large area must be occupied.
本発明の目的は、上記の状況に鑑み、抵抗値を外部から
任意に制御し得る基板占有率のきわめて小さな高抵抗領
域を備えた半導体装置を提供することである。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor device having a high resistance region with an extremely small substrate occupation rate whose resistance value can be arbitrarily controlled from the outside.
本発明によれば半導体装置は、半導体基板と、前記半導
体基板の一主面に絶縁膜を介して形成さ五る高抵抗半導
体層と、前記高抵抗半導体層の両端部にそれぞれオーミ
ック接続される配線電極と、前記配線電極の一方の電位
により制御される前記高抵抗半導体層上のゲート絶縁膜
とを含む。According to the present invention, a semiconductor device includes a semiconductor substrate, a high-resistance semiconductor layer formed on one main surface of the semiconductor substrate via an insulating film, and ohmically connected to both ends of the high-resistance semiconductor layer. The semiconductor device includes a wiring electrode and a gate insulating film on the high-resistance semiconductor layer that is controlled by the potential of one of the wiring electrodes.
以下、図面を参照して本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.
第1図は本発明の一実施例を示す高抵抗領域の断面図で
ある。本実施例によれば、半導体装置は半導体基板1と
、半導体基板の一主面上にフィールド絶縁膜2を介して
被着された高抵抗半導体層3と、高抵抗半導体層3の一
部領域上に設けられたゲート絶縁膜6およびゲート電極
7と、高抵抗半導体層3の一方の端部からコンタクト孔
を介して引出される金属配線4aと、高抵抗半導体層3
の他方の端部からコンタクト孔を介して引出されゲート
電極7と接続される金属配線4bとを含む。ここで、5
は第3図と同じく層間絶縁膜である。このようにゲート
電極7を備える高抵抗半導体層3は両端に加わる電圧に
よる電界効果によってゲート絶縁膜6と接する領域の抵
抗率を変化せしめる。この効果は、例えば厚さ1500
人のポリシリコン層からなる場合は電界効果を生ぜしめ
ない場合の抵抗値2X1011Ω/口に対して約10倍
の1012Ω/口までその抵抗値を高めることができる
程大きなものである。FIG. 1 is a sectional view of a high resistance region showing an embodiment of the present invention. According to this embodiment, the semiconductor device includes a semiconductor substrate 1, a high-resistance semiconductor layer 3 deposited on one principal surface of the semiconductor substrate via a field insulating film 2, and a partial region of the high-resistance semiconductor layer 3. The gate insulating film 6 and gate electrode 7 provided above, the metal wiring 4a drawn out from one end of the high-resistance semiconductor layer 3 through a contact hole, and the high-resistance semiconductor layer 3
A metal wiring 4b is drawn out from the other end of the gate electrode 7 through a contact hole and connected to the gate electrode 7. Here, 5
is an interlayer insulating film as in FIG. In this way, the high-resistance semiconductor layer 3 including the gate electrode 7 changes the resistivity of the region in contact with the gate insulating film 6 due to the electric field effect caused by the voltage applied to both ends. This effect is effective for example at a thickness of 1500
In the case of a human polysilicon layer, the resistance value is so large that the resistance value can be increased to 10<12 >ohms/hole, which is about 10 times the resistance value of 2×10<11 >ohms/hole when no electric field effect is generated.
第2図は本発明の他の実施例を示す高抵抗領域の断面図
である0本実施例によれば半導体基板1と、半導体基板
1の一主面に形成されたフィールド絶縁膜2と、フィー
ルド絶縁膜2の開口部内に端部を接して設けられた半導
体基体1とは逆導電型の半導体層8と、半導体層8の上
面にこれと対向して設けられたゲート絶縁膜6と、ゲー
ト絶縁膜6と一部領域面を接し、また一方の端部を半導
体層8とオーミック接続してフィールド絶縁VIA2上
に延在するように形成された高抵抗半導体層3と、この
高抵抗半導体層3の他方の端部からコンタクト孔を介し
て引出された金属配線4aとを含む。FIG. 2 is a sectional view of a high resistance region showing another embodiment of the present invention. According to this embodiment, a semiconductor substrate 1, a field insulating film 2 formed on one main surface of the semiconductor substrate 1, a semiconductor layer 8 of a conductivity type opposite to that of the semiconductor substrate 1, which is provided in the opening of the field insulating film 2 with its end in contact with the semiconductor substrate 1; A high-resistance semiconductor layer 3 formed so as to be in partial contact with the gate insulating film 6 and to extend over the field insulating VIA 2 with one end ohmically connected to the semiconductor layer 8; A metal wiring 4a is drawn out from the other end of the layer 3 through a contact hole.
本実施例によれば半導体層8は前実施例における金属配
線4bおよびゲート電極7と同様の作用効果を奏し得る
もので、これにかかる電圧による電界効果によってゲー
ト絶縁膜6直上領域の高抵抗半導体層の抵抗率を大きく
変化せしめ得る。According to this embodiment, the semiconductor layer 8 can achieve the same effect as the metal wiring 4b and the gate electrode 7 in the previous embodiment, and the high-resistance semiconductor layer directly above the gate insulating film 6 is caused by the electric field effect due to the voltage applied thereto. The resistivity of the layer can be changed significantly.
以上詳細に説明したように本発明によれば、高抵抗半導
体層の一部領域の抵抗率を配線電圧による電界効果によ
って大きな抵抗値を持つように制御し得るので、基板占
有率のきわめて小さな高抵抗領域を備えた半導体装置を
容易に実現し得る効果を有する。As explained in detail above, according to the present invention, the resistivity of a partial region of the high-resistance semiconductor layer can be controlled to have a large resistance value by the electric field effect caused by the wiring voltage. This has the effect of easily realizing a semiconductor device including a resistance region.
第1図は本発明の一実施例を示す高抵抗領域の断面図、
第2図は本発明の他の実施例を示す高抵抗領域の断面図
、第3図は従来の半導体装置が備える高抵抗領域の断面
図である。
1・・・半導体基板、2・・・フィールド−絶縁膜、3
・・・高抵抗半導体層、4a、4b・・・金属配線、5
・・・層間絶縁膜、6・・・ゲート絶縁膜、7・・・ゲ
ート電極、代理人 弁理士 内 原 音
烏1回
呵31iJFIG. 1 is a cross-sectional view of a high resistance region showing an embodiment of the present invention;
FIG. 2 is a sectional view of a high resistance region showing another embodiment of the present invention, and FIG. 3 is a sectional view of a high resistance region included in a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field-insulating film, 3
...High resistance semiconductor layer, 4a, 4b...Metal wiring, 5
...Interlayer insulating film, 6...Gate insulating film, 7...Gate electrode, Agent Patent Attorney Uchihara Otokarasu 1st Edition 31iJ
Claims (1)
て形成される高抵抗半導体層と、前記高抵抗半導体層の
両端部にそれぞれオーミック接続される配線電極と、前
記配線電極の一方の電位により制御される前記高抵抗半
導体層上のゲート絶縁膜とを含むことを特徴とする半導
体装置。a semiconductor substrate, a high-resistance semiconductor layer formed on one main surface of the semiconductor substrate via an insulating film, a wiring electrode that is ohmically connected to both ends of the high-resistance semiconductor layer, and one of the wiring electrodes. and a gate insulating film on the high-resistance semiconductor layer that is controlled by a potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62058008A JPS63224354A (en) | 1987-03-13 | 1987-03-13 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62058008A JPS63224354A (en) | 1987-03-13 | 1987-03-13 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63224354A true JPS63224354A (en) | 1988-09-19 |
Family
ID=13071941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62058008A Pending JPS63224354A (en) | 1987-03-13 | 1987-03-13 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63224354A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4925518Y1 (en) * | 1969-07-02 | 1974-07-09 | ||
JPS5829939U (en) * | 1981-08-24 | 1983-02-26 | 武田薬品工業株式会社 | Rubber stopper for vial |
JPS5927585B2 (en) * | 1978-10-31 | 1984-07-06 | テルモ株式会社 | Infusion blood transfusion container stopper |
-
1987
- 1987-03-13 JP JP62058008A patent/JPS63224354A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4925518Y1 (en) * | 1969-07-02 | 1974-07-09 | ||
JPS5927585B2 (en) * | 1978-10-31 | 1984-07-06 | テルモ株式会社 | Infusion blood transfusion container stopper |
JPS5829939U (en) * | 1981-08-24 | 1983-02-26 | 武田薬品工業株式会社 | Rubber stopper for vial |
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