JPS63224068A - Time base control system for disk player - Google Patents

Abstract

PURPOSE:To eliminate a pilot signal for controlling a time base by maintaining the rotation of a recording disk at a degree that a synchronizing signal can be detected, even if the synchronizing signal comes not to be detected, and starting immediately controlling the time base by the synchronizing signal when abnormality is disappeared. CONSTITUTION:When an HD signal comes not to be detected because of a drop-out or the like, during a reproducing operation, a PLL servo loop goes to OPEN and simultaneously an F servo loop goes to OFF. Then, similarly to the time of a start, the rotational speed of the disk 1 is set at a value within the range of + or -5% of the prescribed rotational speed so that the detection of the HD signal can be performed again. Thus, the run away of a spindle motor 33 or the like is prevented, and simultaneously, the PLL servo can be drawn in a short time, when the phenomenon of the drop-out is disappeared and the synchronizing signal comes to be detected again. Besides, the time base can be favorably controlled without using the pilot signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a time axis control method for a disc player that reproduces information such as video information recorded on a recording disc.

BACKGROUND TECHNOLOGY MU S compresses high-definition television signals to a bandwidth of approximately 8 MHz to enable transmission by broadcasting satellites.
E (Multiple 5ub-Nyquls
A method called t SampHng Encod 1ng) has been proposed. According to this MUSE system, it is also easy to record high-quality television signals onto a recording medium such as an optical video disc.

However, the synchronization signal of the high-quality image signal (hereinafter referred to as MUSE signal) with a bandwidth of about 8 MHz obtained by this MUSE method is positive polarity synchronization, and the amplitude of the synchronization signal exists within the level of the video signal. . As a result, it is impossible to easily detect the synchronization signal in the MUSE signal using methods such as amplitude separation as in the case of conventional NTSC signals, and the signal must be reproduced on the normal time axis. Synchronous separation is difficult. For this reason, if normal playback is not being performed, especially when the rotation speed is disturbed due to large burst dropouts during playback on an optical video disc player, the disc rotation may be abnormal. This means that the synchronization signal of the video signal cannot be used for time axis control.

Therefore, it has been proposed to frequency-multiplex a pilot signal onto a video FM modulation signal when recording a MUSE signal on a video disk, and to separate this pilot signal during playback to detect time-base errors. However,
Such a method has the disadvantage that it is difficult to remove the influence of the pilot signal on the reproduced image, and at the same time, a circuit for separating and extracting the pilot signal is required, which complicates the configuration of the reproduction apparatus.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a time axis control method for a disc player that can perform time axis control favorably without using a pilot signal.

In the disc player time axis control system according to the present invention, when the synchronization signal is no longer detected, the system responds to the level difference between the reference signal according to the radial position of the signal reading means and the speed detection signal according to the rotational speed of the recording disc. The present invention is characterized in that the time axis is adjusted using the error signal obtained by the synchronization signal, and when the synchronization signal is detected, the time axis adjustment is started again using the error signal according to the phase difference between the synchronization signal and the reference signal.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, recorded information on a disc 1 is read by an optical pickup 2. As shown in FIG. The pickup 2 includes a laser diode, an objective lens, a focus actuator, a tracking actuator, a photodetector, and the like.

The output of the photodetector in the pickup 2 is supplied to an RF amplifier 3 and a tracking error generation circuit 4. A tracking error generation circuit 41 generates a tracking error signal using a three-beam method, a push-pull method, or the like.

This tracking error signal is supplied to the tracking actuator in the pickup 2 via the tracking servo amplifier 5. Further, the DC component of the tracking error signal is supplied via a slider servo amplifier 6 to a slider motor 7 that moves a slider carrying a pickup 2 in the disk radial direction.

The tracking error generation circuit 4, the tracking servo amplifier 5, and the slider servo amplifier 6 detect information that is formed when a laser beam emitted from a laser diode in the pickup 2 is focused on the recording surface of the disk 1 by an objective lens. The position of the optical spot (information detection point) in the radial direction of the disk 1 is controlled.

A drive signal output from a search operation control circuit 7 is supplied to the slider servo amplifier 5. The search operation control circuit 7 receives data indicating the number of moving tracks from the system controller 8, and specifies the information detection light spot while counting the number of tracks to which the information detection light spot has skipped and moved based on the tracking error signal. The slider servo amplifier 6 is configured to send a drive signal to the slider servo amplifier 6 until the slider servo amplifier 6 has moved by the number of tracks set, and then output a movement end signal. Further, a track jump command signal is supplied from the system controller 8 to the tracking servo amplifier 5, so that the information detection light spot jumps one track at a time.

On the other hand, the RF (high frequency) signal output from the RF amplifier 3 is supplied to a demodulation circuit 9 consisting of an FM demodulator etc.
The SE signal is demodulated. After the amplitude of this MUSE signal becomes constant (for example, 1Vp-p) by a clamp circuit 10 and an AGC (automatic gain control circuit) 11, the A/D
(analog-digital) converter 12 and comparator 13. The A/D converter 12 is supplied with a 16.2 MHz clock a output from the pulse generating circuit 14. In the A/D converter 12, the MUSE signal is sampled by the clock a, and the obtained sample values are sequentially converted into digital data. The output data of this A/D converter 12 is transmitted to an HD detection OK signal generation circuit 15, an FP detection circuit 16,
At the same time as being supplied to the data separation circuit 17, it is sent to a MUSE decoder (not shown).

The FP detection circuit 16 is configured to detect frame pulses in the digitized MUSE signal output from the A/D converter 12, for example, by pattern recognition. That is, when the FP detection circuit 16 detects the frame pulse inserted in the portion corresponding to the 605th line of the MUSE signal by pattern recognition, the FP detection circuit 16 detects the frame pulse inserted in the 606th line of the MUSE signal.
The pattern of frame pulses shown in FIG. 2 (A), which are inserted into the portion corresponding to the line and whose phase is inverted, is sequentially recognized by the clock a shown in FIG. A frame pulse point p existing a minute ahead is detected to generate an FP detection pulse b as shown in FIG.

FP detection pulse b output from this FP detection circuit 16
is supplied to the FP counter 18. FP counter 18
is configured to count the number of pulses of clock a over the period between two consecutive FP detection pulses.

This FP counter 18 obtains a count value NF corresponding to the generation cycle of the FP detection pulse. This FP counter 1
The output data of 8 is supplied to a divider 19 to calculate the average number of clocks NHD (NF/1125) in the HD interval. At normal timing (synchronized and without jitter), the detection FP interval is 540,000 clocks (
480 clocks xl125) exist, but if the rotational speed of the disk is controlled with an accuracy of a few percent of the specified speed, the average value of the HD interval is calculated by dividing the number of clocks NF existing during the detection FP interval by 1125. It is obtained by

The output data of the divider 19 is supplied to the HD detection OK signal generation circuit 15 and the HD detection circuit 20.

The HD detection OK signal generation path 15 generates an HD detection window signal having a pulse width of 16 clocks centered at a position delayed by 13 clocks from the rising edge of the FP detection pulse b, for example, and when this HD detection window signal exists. The HD detection OK signal is generated according to the level indicated by the output data of the A/D converter 12 during a period of 16 clocks. That is, the HD detection OK signal generation circuit 15 operates as shown in FIG. 3(D) over a period of 16 clocks centered at a position 13 clocks away from the rising edge of the FP detection pulse b as shown in FIG. 3(C). During the 6-clock period during which the HD detection window signal as shown in the figure exists, the output data of the A/D converter 12 as shown in FIG.
After reaching the value corresponding to the 58 level, it becomes the value corresponding to the 84/258 to 192/258 level over the next two clocks, and then becomes 64/25 over the next two clocks.
When the value corresponding to 1 level is reached, the HD detection OK signal is output for, for example, 4 clocks from the rise of the next clock a between the 2 clocks in which the 84/256 level was detected, as shown in (E) in the same figure. generate d. Thereafter, HD detection is performed in the same manner, but the timing for generating the next HD detection window signal is set using the NHD calculated by the divider 19.

That is, HD detection from the 608th line onward starts from the rise of the HD detection OK signal on the 607th line mentioned above.
This is done by generating a detection window signal that exists for 16 clocks centered on a position delayed by -3 clocks. Note that since the HD double signal is inverted for each line after the 607th line, HD detection is also inverted accordingly. Also,
N) 4D is updated sequentially as FP detection is performed, so NF also uses F servo (frequency servo), which will be described later.
As the loop locks it approaches 480x1125 (clock).

Also, if the HD signal is lost due to dropouts, etc.
The D detection OK signal d does not rise and there is no timing to generate the next HD detection window signal, but since the time width of the HD detection window signal is set to 16 clocks, for example, the previous HD detection window signal It is sufficient that the signal is generated over a period of 16 clocks centered at a position delayed by N1-ID from the center of the clock.

The HD detection OK signal d is supplied to the HD detection circuit 20. The HD detection circuit 20 maintains a high level for a predetermined period of time from the rising or falling edge of the output of the delay circuit 21 which delays the output of the comparator 13 by about 5 clocks when the HD detection OK signal is present. HD detection signal e
is configured to output.

Now, the MUSE signal output from the FM demodulation circuit 9 passes through the clamp circuit 10 and the AGC circuit 11, and is supplied to the comparator 13 as a signal having an amplitude of 1V peak-to-peak as shown in FIG. 4(A). This comparator 1
If the reference level 3 is set to the center level of the amplitude of the output f of the AGC circuit 11, that is, the level corresponding to the 128/256 level, the output of the comparator 13 will always be inverted at the slope part of the HD signal, as shown in the figure. A signal as shown in (B) is obtained. Since the HD signal is a line alternating signal, rising edges and falling edges alternately appear in the output of the comparator 13 in the same period as the IH. However, since level inversion occurs frequently in the video signal, edges in the HD signal are detected using the ID detection OK signal d (as shown in FIG. 2C).

That is, the output g of the comparator 13 is
As shown in FIG. 3(D), the edge of the HD signal is a signal that appears at the center timing of the existence period of the HD detection OK signal d in the normal state (locked state). Therefore, the delay amount of the delay circuit 21 is approximately 5
The time is set to a clock minute. If anything, H
This is because the D detection OK signal d is generated approximately three clocks later than the slope portion of the HD signal, and has a signal width of four clocks. In addition, in this example, as described later, F
Since the rotational speed of the disk 1 is controlled by the servo loop to a value of approximately ±5% of the specified speed, the timing of the HD detection OK signal d is within ±1 clock accuracy of the specified timing, and 12 from the characteristics of HD waveforms
Since the output g of the comparator 13 is not inverted within ±4 clock widths with respect to the 8/256 level, the width of the HD detection OK signal d is set to 4 clock widths.

For HD detection, the output timing of the HD detection signal is determined by the level inversion edge of the delayed output of the comparator 13 that exists within the HD detection OK signal width, and the pulse width is set to approximately 0.5 HD intervals using a one-shot circuit or the like. As a result, during locking, an HD detection signal e as shown in FIG. 2(E) consisting of a 50% duty pulse is generated.

In addition, if the HD detection OK signal is not output due to dropout, it is forced to 1 at the N1-ID timing: H
What is necessary is to generate a D detection signal. Further, the delay circuit 21 causes a dead time element to exist in the time axis servo loop, but this does not cause any problem because the bands of the spindle system and the jitter control system are about ten-odd Hz and several kHz, respectively.

The detection output of the HD detection circuit 20 is supplied to a phase comparison circuit 21 to generate an error signal according to the phase difference with the output of the frequency division circuit 23. The frequency dividing circuit 23 is configured to frequency divide the clock pulse and generate a reference signal of a predetermined frequency. The output of the phase comparator circuit 21 is supplied to a selector switch 26 via an equalizer amplifier 25. Further, the output of this phase comparison circuit 21 is supplied to a lock detection circuit 27. The lock detection circuit 27 is configured to generate a PLL lock detection signal when the absolute value of the output of the phase comparison circuit 21 becomes less than or equal to a predetermined value. This PLL lock detection signal is supplied to the system controller 8.

The output of the changeover switch 26 is supplied as a spindle error signal to a spindle motor 33 that rotationally drives the disk 1 via a drive amplifier 32, so that the rotational speed of the disk 1 is controlled. The spindle motor 33 has a built-in frequency generator 34 that generates an FG multiplied signal of a frequency corresponding to the rotational speed of the spindle motor 33. FG multiplied signal output from this frequency generator 34, waveform shaping circuit 35
The signal is supplied to an F/V converting circuit 36 including a differentiating circuit or the like, and is converted into a signal having a signal level corresponding to the FG multiplied signal frequency. The output of this F/V conversion circuit 36 is supplied to a subtraction circuit 37.

The subtraction circuit 37 has a D/A (digital analog)
The output of the converter 38 is supplied, and the output of the F/V conversion circuit 36 is subtracted from this D/A converter 38. The output of the subtraction circuit 37 is supplied to the lock detection circuit 39 and at the same time becomes a low input of the changeover switch 26 via an equalizer amplifier 40.

The changeover switch 26 is configured to selectively output one of the outputs of the equalizer amplifiers 25 and 40 according to a command supplied from the system controller 8. The lock detection circuit 39 also includes, for example, a subtraction circuit 37.
The F servo lock detection signal is generated when the absolute value of the output becomes equal to or less than a predetermined value. The output of this lock detection circuit 39 is supplied to the system controller 8. The system controller 8 is supplied with address information inserted into a predetermined section of the MUSE signal by the data separation circuit 17, that is, a frame number in a CAV disk or a time number in a CLV disk. The system controller 8 is formed by a microcomputer including a processor, R, OMSRAM, timer, and the like. In this system controller 8, each part is controlled by a processor that operates according to a program stored in advance in a ROM.

The operation of the processor of the microcomputer that forms the system controller 8 in the above configuration will be explained with reference to the flowcharts of FIGS. 5 and 6.

When a play command is issued by operating a key on the operation unit (not shown) during execution of a main routine, etc., the processor moves to step S1 and stores the rotational speed FO of the disk 1 at the reading start position (innermost circumference) in the ROM. Calculated using a table stored in advance. Next, the processor moves to step S2 and sends the rotational speed data to the D/A converter 38. The processor then performs step S
3 and from the changeover switch 26 to the equalizer amplifier 4.
The frequency generator 34, the waveform shaping circuit 35, the F/V conversion circuit 36, the subtraction circuit 37, the equalizer amplifier 40, the changeover switch 26, the drive amplifier 32, and the spindle motor 33 are configured such that the output of 0 is selectively output. Turn on the F servo loop that will be formed. Next, the processor moves to step S4 and determines whether or not the F servo lock detection signal is output from the lock detection circuit 39.

In step S4, when it is determined that the F servo lock detection signal is not output, the processor executes step S4 again, and only when it is determined that the F servo lock detection signal is output, the processor moves to step S5. Then, it is determined whether the HD detection OK signal is output.

If it is determined in step S5 that the HD detection OK signal is not output, the processor returns to step S5.
Step S6 is executed, and only when it is determined that the HD detection OK signal is output, the process moves to step S6. Step S6
In the step, the processor selectively outputs the output of the equalizer amplifier 25 from the changeover switch 26.
HD signal and frequency divider 2 at the same time as turning off the servo loop
The PLL servo loop that controls the rotational speed of the spindle motor 33 according to the phase difference with the output of No. 3 is turned on. Next, the processor moves to step S7 and determines whether or not the PLL lock detection signal is output from the lock detection circuit 27. When it is determined in step S7 that the PLL lock detection signal is not output,
The processor executes step S7 again, and only when it is determined that the PLL lock detection signal is output, moves to step S8, sends an operation start command to a MUSE decoder (not shown), etc., and starts playback operation. Let, step S
Resumes execution of the routine that was being executed immediately before transitioning to step 1.

Further, during the execution of a main routine or the like, an interrupt by a timer or the like causes the processor to proceed to step S11 and determine whether or not a reproduction operation is in progress.

If it is determined in step S11 that the playback operation is not in progress, the processor resumes execution of the routine that was being executed immediately before proceeding to step S311. Step S
When it is determined that the playback operation is in progress in ll,
The processor moves to step S12 and detects the current reading position based on the output of the data separation circuit 17. Next, the processor proceeds to step 813 and calculates the prescribed rotational speed Fn of the disk 1 at the detected reading position using a table stored in advance in the ROM.

Next, the processor moves to step S14 and sends the rotational speed data Fn to the D/A converter 38. Next, the processor moves to step S15 and detects the HD.
It is determined whether the K signal is output. Step S
If it is determined in step S15 that the HD detection OK signal has been output, the processor proceeds to step S16, resets the timer flag, and resumes execution of the routine that was being executed immediately before proceeding to step S11. .

If it is determined in step S15 that the HD detection OK signal is not output, the processor proceeds to step S17 and determines whether or not the timer flag is set. If it is determined in step S17 that the timer flag is not set, the processor moves to step S18, sets the timer time to a time corresponding to, for example, the HD interval, and starts the timer operation. Next, the processor moves to step S19, sets a timer flag, and moves to step S15 again. If it is determined in step S17 that the timer flag is set, the processor proceeds to step S20 and determines whether or not the timer's timing operation has ended.

If it is determined in step S20 that the time counting operation of the timer has not ended, the processor returns to step S20.
15. When it is determined in step S20 that the time counting operation of the timer has ended, the processor moves to step S21, resets the timer flag, and moves to step S22. In step S22, the processor sends an operation stop command to a MUSE decoder (not shown) or the like to stop the reproduction operation.

Thereafter, the processor executes steps S23 to S28 similar to steps 83 to S8, and resumes execution of the routine that was being executed immediately before proceeding to step S11.

In the above operation, when a play command is issued, the output of the equalizer amplifier 40 is selectively outputted from the changeover switch 26 in step S3, and the F servo loop is turned on. Then, in step S2, D/
Since data corresponding to the rotation speed of the spindle motor 33 at the reading start position is supplied to the A converter 38,
The spindle motor 33 is driven and controlled so that the rotational speed of the disk 1 converges to a specified speed at the reading start position. With this F servo, the rotational speed of the disk 1 can be adjusted to a value within the range of ±5% of the specified rotational speed so that the HD signal can be detected.

Now, if the detection level in the lock detection circuit 39 is set so that the F servo lock detection signal is generated when the rotation speed of the disk falls within the range of ±5% of the specified rotation speed, the F servo lock detection signal will be generated. When this occurs, the PLL servo loop is turned on in steps S5 and S6, and the rotational speed of the spindle motor 33 is controlled so that the phase of the HD detection signal and the reference signal output from the frequency divider 23 match, Highly accurate time axis control will begin.

When the HD signal cannot be detected due to dropout or the like during playback operation, it is recognized in steps S15 to S20 that the HD signal cannot be detected, and the Mechitub 823 turns the PLL servo loop into an oven and simultaneously switches the F servo. The loop is turned on, and the rotation speed of disk 1 is kept within ± of the specified rotation speed, just like at startup.
The HD signal can be detected again by setting the value within the range of 5%. Therefore, even if the HD signal cannot be detected due to dropout, etc., it prevents the spindle motor from running out of control, and at the same time, when the dropout phenomenon disappears and the synchronization signal is detected again, the PLL servo can be pulled in for a short time. This means that it can be done.

Note that the method of controlling the rotational speed of the spindle motor 33 using the F servo loop as in steps S1 to S4 and S11 to S24 can also be employed in an apparatus that performs time axis control using a pilot signal.

Effects of the Invention As detailed above, in the time axis control method according to the present invention, when a synchronization signal is no longer detected, a reference signal corresponding to the radial position of the signal reading means and a speed detection signal corresponding to the rotational speed of the recording disk are generated. The time axis is adjusted using an error signal according to the level difference between the synchronous signal and the reference signal, and when the synchronous signal is detected, the time axis is adjusted again using an error signal according to the phase difference between the synchronous signal and the reference signal. Even if the synchronization signal is no longer detected due to an error, etc., the rotation of the recording disk can be maintained to the extent that the synchronization signal can be detected, and the time axis adjustment using the synchronization signal can be started immediately when the abnormality such as dropout disappears. This eliminates the need for a pilot signal for time axis control. Therefore, during normal reproduction, a good reproduced image without interference caused by the pilot signal can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 to 4 are waveform diagrams showing the operation of the device in FIG. 1, and FIG.
6 are flowcharts showing the operation of the processor of the microcomputer forming the system controller 8 in the apparatus shown in FIG. I watched it three times and went to the 7th layer.
C 但 (JQ uJ ま, 5th figure

Claims (2)

[Claims] (1) Detecting a synchronization signal from a signal obtained by a signal reading means for reading a recording signal of a recording disk, and generating a first error signal according to a phase difference with a first reference signal, and using the first error signal A time axis control method for a disc player that adjusts the time axis, when the synchronization signal is no longer detected, the time axis adjustment based on the first error signal is stopped, and the radial position of the signal reading means is adjusted. generating a second error signal according to a level difference between a second reference signal corresponding to the rotational speed of the recording disk and a speed detection signal corresponding to the rotational speed of the recording disk, and controlling the rotational speed of the recording disk according to the second error signal. 1. A time axis control method for a disc player, characterized in that when the synchronization signal is detected, the time axis adjustment according to the first error signal is started again. (2) The recording signal is a MUSE (M
ultipleSub-NyquistSamplin
2. The time axis control method for a disc player according to claim 1, wherein the synchronization signal is a horizontal synchronization signal (HD signal).