JPS63223837A - Queued spare type duplex processor system - Google Patents

Abstract

PURPOSE:To minimize the service interrupting time when systems are switched while confirming the normal state of a duplex system, by using one of shared memory devices free from double writing as a saving area when a test is carried out for confirmation of the normal state of a program storing memory device. CONSTITUTION:When a test is carried out for confirmation of the normal state of a program storing memory device 6 of a spare queued processor 2, the contents of a test subject area are saved to a shared memory device 8 set at the queued side. Then the test subject area is tested. When this test is through, the contents of the test subject area are restored based on the saved contents. When a processor 1 of an on-line system has a fault and switched to the processor 2, the continuation of the on-line processing is tried via a CPU 4, the device 6 and a shared memory device 7 set at the present on-line side. If the memory restart fails, the on-line processing is carried out by means of the device 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a standby standby type dual processor system, and more particularly to testing of a memory device for storing a program of a standby processor and improvement of a system switching system.

[Conventional technology]

Traditionally, methods for duplicating processors include a synchronous operation method that performs synchronous verification at the microinstruction level, and a standby method that connects the active system and standby system with a shared memory or shared disk that can be accessed from both systems. However, the former synchronous operation method has the problem that the hardware configuration is complicated due to synchronous verification at the microinstruction execution level, and that a general-purpose CPU cannot be used in one system. Therefore, in a system where such a problem cannot be ignored, the latter standby system is exclusively used. During the period when a program is loaded into the processor's program storage memory device by IPL (initial program load) by down line loading from an external storage device or host device, and actual work such as online processing is performed in the active system. , tests are conducted to confirm the normality of various memory devices of the backup processor. In this normality confirmation test, when a program storage memory device is tested, conventionally the memory contents remain rewritten during the test. Therefore, when switching systems, it is necessary to reload the program from an external storage device etc. to the program storage memory device.
Coupled with the recent trend of increasing the capacity of programs to be loaded, there has been a drawback in that service interruption time associated with system switching increases.

The present invention has solved such conventional drawbacks, and its purpose is to prevent the contents of the program storage memory device from being rewritten during the normality confirmation test of the memory device of the standby processor, and to quickly update the memory device. The objective is to enable easy system switching.

[Means for solving problems]

In order to achieve the above object, the present invention provides a standby/standby type dual processor system in which one processor is used as the active system and the other processor is on standby as the standby system, in which access is possible from both systems which are duplexed but do not have dual writing. The processor has a shared memory device, and the normality confirmation test of the program storage memory device in the standby processor is performed after the contents of the test target area are saved to the standby shared memory device among the duplicated shared memory devices. and the saved contents are restored from the shared memory device to the program storage memory device upon completion of the normality confirmation test of the test target area, and at the time of system switching, the backup system processor The processor is configured to attempt to continue processing by using the shared memory device originally used by the active processor among the duplicated shared memory devices.

[Effect]

Duplicated shared memory devices are used, for example, to store online transaction data, and when testing the normality of a program storage memory device in a standby processor, the contents of the test target area are transferred to one of the shared memory devices. This is done while saving and restoring using the shared memory device on the side, and when switching systems, an attempt is made to continue processing such as online processing using the shared memory device used by the active processor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
are each a processor, and while one is in online operation, the other is on standby as a standby system. Also, 3 and 4 are CPUs, 5
and 6 are memory devices for storing programs, and 7 and 8 are shared memory devices for storing transaction data that can be accessed from both systems. Note that 9 and 10 are buses.

In FIG. 1, PL to program storage memory devices 5 and 6 in each processor 1 and 2 is performed simultaneously by down line loading from an external storage device or host device (not shown). When Bromo 7S 1 is the active system, its CPU 3 performs online processing according to the program stored in the program storage memory device 5, using the shared memory device 7 as an online transaction data storage memory. At this time, the shared memory device 8
is on standby as a spare device for the shared memory device 7,
Duplication of content will not occur.

Processor 2 is on standby as a standby system, and while it is on standby, the standby CPU 4 performs a health check on hardware such as memory devices under instructions from processor I, and the results are sent to the processor. Reported to 1.

Incidentally, the program storage memory device 6 is composed of a ROM section and a RAM section, and in the normality confirmation test of the RAM section of the program storage memory device 6 by the CPU 4, the test target area is rewritten. Therefore, in this embodiment, when the processor 2 performs a normality confirmation test on the RAM section of the program storage memory device 6, the contents of the test area are shared with the standby side as shown in the flowchart of FIG. The contents of the test area are saved to the memory device 8 (SL), then the test area is tested (S2), and after the test is finished, the contents of the test area are restored based on the contents saved to the shared memory device 8 (S
3). This prevents the contents of the program storage memory device W6 from being destroyed by the normality confirmation test as in the conventional case. Note that a normality confirmation test for the shared memory device 8 is also performed, but since the shared memory device 8 is not involved in online processing, a simple rewriting test can be performed.

Now, when a failure occurs in the online system processor 1 and a switchover is made to the processor 2 side as is well known, the CPU 4 . An attempt is made to continue the online processing using the program storage memory device 6 and the currently online shared memory device 7. Then, only when this memory restart fails, the program storage memory device 6 is IPLed again, and online processing is performed using the shared memory device 8.

FIG. 3 is a flowchart showing an example of processing performed by the processor 2 at the time of switchover. When the processor 2 is instructed to switch systems along with the necessary information, it determines whether or not the normality confirmation test of the RAM section of the program storage memory device 6 is currently being performed, and therefore it is necessary to restore the test area. If necessary, the process proceeds to step S13, but if necessary, the test area of the program storage memory device 6 is restored based on the contents saved in the shared memory device 8 (S12), and online processing is performed. After performing the initial setting processing of each part necessary for execution (313), an attempt is made to continue the online processing using the shared memory device 7 on the current online side (514). If the memory is successfully restarted through this trial, online processing using the shared memory device 7 continues.
If the memory restart fails, the program storage memory device 6 is re-IPLed (S16), and after performing the initial setting process of each part necessary for online processing execution (S16).
17) Execute online processing using the shared memory device 8.

〔Effect of the invention〕

As explained above, the present invention uses one of the shared memory devices that does not allow double writing as an evacuation area during the normality confirmation test of the program storage memory device, thereby confirming the normality of the hardware. This has the effect of minimizing service interruption time during system switching.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flowchart of an example of test processing of processor 2, and FIG. 3 is a flowchart of an example of processing when switching from standby system to active system of processor 2. be. In the figure, 1.2...processor, 3,4...C
PU, 5.6... Memory device for storing programs, 7゜8... Shared memory device, 9. lO... bus.

Claims (1)

[Scope of Claims] In a standby/standby type dual processor system in which one processor is used as an active system and the other processor is on standby as a standby system, there is provided a shared memory device that can be accessed from both systems that are duplexed but do not have dual writing. However, the normality confirmation test of the program storage memory device in the standby processor is performed after the contents of the test target area are saved to the standby shared memory device of the duplexed shared memory devices, and the test target area is The evacuated contents are restored from the shared memory device to the program storage memory device upon completion of the area normality confirmation test, and when switching systems, the standby processor is configured to restore the saved contents from the shared memory device to the program storage memory device. 1. A standby and backup dual processor system, characterized in that the active processor of the device attempts to continue processing using the shared memory device that was originally used.