JPS63221492A - Graphic processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a graphic processing device, and particularly to a graphic processing device suitable for calculating xy coordinates and display memory addresses for the coordinates.

[Prior Art] Conventionally, graphic processing devices calculate XY coordinates and calculate the
There are known devices that perform drawing while calculating memory addresses. According to the known example, the arithmetic unit that performs the coordinate calculation and the arithmetic unit that performs the memory address calculation are controlled by a common microprogram.

On the one hand, the algorithms for drawing figures are complex;
The microprogram that describes the algorithm also becomes complex. Therefore, during processing, it may be necessary to branch in multiple directions depending on conditions such as parameters. According to the above-mentioned conventional technology, a means for performing two-way branching at high speed is provided, but there is no method for efficiently performing multi-directional branching, and when branching in multiple directions, it is necessary to use two-way branching frequently. there were.

Furthermore, when a complex microprogram is written, the efficiency of program creation is greatly influenced by the method of debugging the program. Therefore, it is important to have an effective depacking method.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, a common microprogram controls a calculation unit that performs coordinate calculations and a calculation unit that performs memory address calculations. Therefore, the description of the microprogram involves a mixture of algorithm description and memory address description, which poses a problem in improving the descriptive performance.

On the other hand, there is no consideration given to multidirectional branching;
There were problems with program description and high speed.

Further, no consideration was given to program depacking, and there was a problem with debugging efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a graphic processing device that separates a microprogram that performs coordinate calculations and a microprogram that performs memory address calculations, thereby improving program descriptiveness.

Another object of the present invention is to provide a graphic processing device having an efficient multi-directional branching method for microprograms.

Another object of the present invention is to provide a method for debugging a microprogram, in which a microprogram being executed is stopped at a desired address, internal information of the graphic processing device is read out, and after the internal information is read out in this manner, the microprogram being executed is stopped at a desired address. An object of the present invention is to provide a graphic processing device having an effective debugging method by making a stopped program run again.

[Means for solving problems]

The above object is to separately provide a microprogram for controlling coordinate calculations and a microprogram for controlling memory address calculations, and to cause the microprograms for controlling the coordinate calculations to operate the microprograms for controlling the memory address calculations. After working like this,
The microprogram that controls the memory address is
In addition to allowing the program to proceed independently, if there is a request for further operation while the microprogram controlling the memory address calculation is operating, the microprogram controlling the memory address calculation This is achieved by providing a means for stopping the program until the processing is completed.

Another object of the above is to provide means for storing information for multi-directional branching of the microprogram that controls the coordinate calculation, and means for storing the effective number of bits of the means, and to store a jump address in an address register. This is achieved by placing only the bits designated by the means for storing the number of effective bits in place of the jump address with the data of the means for storing information for making the multidirectional branch.

The other object described above is a means for storing an address for stopping a microprogram that controls the coordinate calculation;
This is achieved by comparing the means for storing the address to be stopped with the address of the microprogram and outputting a signal when they match, and using the match signal as a set or reset signal for the address register. .

[Effect]

By separately providing a microprogram that controls coordinate calculations and a microprogram that controls memory address calculations, it is possible to write a drawing algorithm in the microprogram that controls the coordinate calculations, and the program description It is possible to improve sexual performance.

The number of branches can be made variable by providing means for storing information for performing multi-branching of a microprogram and means for indicating an effective bit of the means.

By providing means for storing an address for stopping the microprogram, and means for comparing the means and the address of the microprogram and outputting a match signal, and using the match signal to generate a unique value in the address register of the microprogram, A microprogram can be stopped and debugged.

〔Example〕

FIG. 1 is a block diagram of a graphic processing device according to the present invention.

In the figure, the graphic processing device includes a logical address calculation unit 310 that calculates drawing coordinate points as x and Y coordinate values, a physical address calculation unit 320 that calculates a memory address corresponding to the coordinate values, and a physical address calculation unit 320 that calculates drawing data. The color data calculation section 330 is broadly divided into a color data calculation section 330.

The logical address calculation unit 310 mainly calculates where the drawing point is on the screen according to the drawing algorithm, and includes the logic microprogram ROM 210, the logic microinstruction register 260, and the logic microinstruction degoder 2.
70, logic microprogram ROM address register (1, RAR) 220, address incrementer (
I NC) 230° stack 240, instruction register 2
50, multi-jump control (MJC) 180, break point register (BPR) 160, -number configuration circuit 15
It consists of 0.

Physical address calculation unit 320 and color data calculation unit 330
is controlled by a physical microprogram ROM 100,
Other physical microinstruction registers 120, physical microinstruction decoder 130, physical microprogram ROM address register 110. WAIT control 140.

Also, an intermediate buffer 17 for transferring data between the logical address calculation unit 310 and the physical address calculation unit 320
0, and an internal RAM 340 that stores calculation parameters, line type information, pattern information for painting, and the like.

FIG. 2 shows details of the logical address calculation unit 310. With FIF○ buffer 3101.

Multi-jump register (MJR), 3100, and general-purpose register group (TROX, TR0Y, TRIX.

TRIY, TR2X, TR2Y, TR3X, TR3Y)
3102, drawing coordinate current pointers (CPDX) 3103 and 3104 (CPDY) pointing to drawing coordinates,
Transfer source coordinate current pointer (CPS) that points to the transfer source coordinate
X) 3105 and 3106 (CPSY) and area management register (XMIN) 3107°3108 (YMIN)
, 3111 (XMAX) and 3112 (YMA)
and area determination comparators (ACMPN) 3109 and 311
0 (ACMPX) and the end point register (X, E ND
) 3113 and 3114 (YEND), end point comparator (ECMP) 3115, source latch (S F
T, HEXSFT, SLAV) 3117 and (SLAU) 3116, and arithmetic logic unit (ALU)
3118 and destination latch (DLA) 31
19, constant generator (LITERAL) 3123,
Read bus (UBA.

VBA) 3120 and 3121 and write bus 3122
It is equipped with

Further, FIG. 3 shows details of the intermediate buffer 170 and the physical address calculation unit 320.

Internal RAM buffer (RBUF) 320 and general-purpose register group (TDRO, TDRI, TDR2°TDR3) 32
05, 3206, 3207, and 3208, and a register (DRAD) 32 that stores the memory address of the drawing coordinate system.
12, a register (DRAS) 3213 that stores the memory address of the transfer source coordinate system, a register (PTNA) 3214 that points to the memory address of the pattern coordinate system that stores the fill pattern of the figure, and a bell area for drawing thick lines. Pointing register (PLA) 3215 and general-purpose register
(TAO, TAI) 3216 and 3217, and a register (CMWD) 3218 that stores the memory width of the drawing coordinate system.
and a register that stores the memory width of the source coordinate system (C
MWS) 3219, a register (PMW) 3220 that stores the memory width of the pattern coordinate system, pattern control registers (PS, PE, PP) 3221, 3222 and 3223, and a pattern that updates the pattern pointer (PP) 32.23. Pointer counter (PCNT) 3224
and source latch (SLBU) 3225 and (S L
B V) 3226, arithmetic unit (AU) 3227, barrel shifter (BRLSFT) 3228, data expander (DE) 3229, and multiplexer (MPX)
3230 and destination latch (DLB) 32
31 and read buses (UBB, VBB, UBC.

VBC) 3232, 3233.3235 and 3236 and write bus (WBB, WBC) 3234 and 3237
and bus switch 3201, 3202゜3203.32
09.3210 and 3211.

Further, FIGS. 4 and 5 are detailed diagrams of the color data calculation section. The color data calculation unit 330 is connected to the multiplexer 3
304 and a color register (CLO.

CLI) 3305 and 3306, color comparison register (
CLCMP) 3307 and edge color register (ED)
G) 3308 and drawing mode register (DM) 3309
and a mask register (GMASK).

SMASK, EMASK, TMASK, ItlMASK
.

RMASK) 3311, 3312, 3313°3314
．． 3315 and 3316, a color comparator 3317,
A zero flag extender (ZE) 3318, a carry flag extender (CMPMSEL) 3320, and a destination latch (DLC) 3321.

Arithmetic logic unit (ALU) 3322, write data buffers (WDBR(M), WDBR(S)) 3223 and 3224, and read data buffer (RDBR) 3
325 and internal RAM address definition register (IRA
R) 3327, -number of bases on base 3328, stack area definition register (SSDR) 3329, -number of bases on base 33
30 and stack start address register (SSAR) 3
331, memory address registers (MAR(M), M
AR(S)) 3332 and 3333, - several bases on base 33
34, a mask bus (MSKB) 3310, a color data bus (CLB) 3301, and a memory input/output bus 32.
37, an address output bus 3335, a memory address bus (MAB) 3338, and a traffic buffer 3336.

Next, the operation of the embodiment configured as described above will be explained. First, a two-level microprogram, which is one of the features of the present invention, will be explained.

In FIG. 1, an instruction code from an external device such as a central processing unit (not shown) written to the instruction register via the FIFO 350 is stored in the logic microprogram ROM 210.
LRAR2 enters the LRAR220 to read out the LRAR2.
According to the address set to 20, the logic microinstruction is read out, and the logic microinstruction thus read out enters the logic microinstruction register 260. Thereafter, the logical micro-instruction is decoded by the logical micro-instruction decoder 270, which controls the logical address calculation section 310 to calculate a logical address. Meanwhile, the value of LRAR 220 is updated by address incrementer (INC) 230, and the logical microinstructions are read out in sequence accordingly. Further, when using a subroutine, a return address from the subroutine is set in the stack 240.

On the other hand, the logical microinstruction reads the physical microprogram ROM 100 in order to calculate the physical address corresponding to the logical address.

The physical microinstructions are for controlling the physical address calculation unit 320 and the color data calculation unit 330. A portion of the logical microinstruction goes into PRARIIO and becomes the address from which the physical microinstruction is read. PRARIIO above
The physical microinstruction read according to the physical microinstruction register 120 is read. The physical microinstruction is then decoded by a physical microinstruction decoder 130.

Controls the physical address calculation unit 320, calculates the physical address, reads data in the display memory using the physical address, performs color data calculation in the color data calculation unit 330, and writes the calculated data to the display memory. It's crowded.

FIG. 6 shows an example of a program in which the microprogram for logical address calculation and the microprogram for physical address calculation are separated into two levels as described above. An example of drawing a value line (a > b) as shown in (C) is shown in (a) as an example of a logic microprogram, (
b) is shown as an example of a physical microprogram. A feature of this embodiment is that the flow in (a) is only a description of an algorithm for calculating a logical address, which improves the writeability of a microprogram and reduces writing errors. The physical microprogram can independently advance the program sequence when activated by the logical microprogram. When a startup request is received from a logical microprogram while the physical microprogram is being executed, the WAIT control unit 140 issues a request to the logical microprogram.
An operation stop signal (wait signal) is issued, and the logical microprogram is stopped until the physical microprogram stops operating.

Another feature of this embodiment is that the physics microprogram has many descriptions that are not affected by the drawing algorithm, so the description shown in FIG. It can also be applied to drawings such as As a result, compared to the method shown in Japanese Patent Application No. 59-251907, in which a logic microprogram and a logic microprogram were written as the same microprogram,
The microprogram capacity in this embodiment can be substantially reduced.

Next, multi-branch control (multi-jump), which is another feature of the present invention, will be described.

In the logic microprogram ROM 210 that describes the drawing algorithm, it may be necessary to perform multi-directional branching due to differences in parameters.

In such a case, it is possible to perform faster processing by branching in multiple directions at once than by using two-way branches multiple times. Therefore, in the embodiment, a method will be described that allows multi-directional branching and increases the number of branches.

- Figure 7 shows the flow when branching using this method. First, set the number of branches. The feature of this method is that the number of branches can be set in units of 2 to the nth power, and the interval between one branch destination address can also be changed. For example, when performing a four-way branch, the address interval for each branch destination can be set at intervals of 2 to the nth power from 4 addresses to 512 addresses. The address space can be used effectively by changing the address interval of the branch destination depending on the size of the program amount of the branch destination.

8 and 9 illustrate the above system.

The number of branches is set in each register of the multi-jump control register 1801 in the multi-jump control circuit 180. Information for branching is set in multi-jump register (MJR) 31.00. Then from the logic microprogram, when the jump address is set to LRAR220, the multi-jump control register 1
Only bits with It I It set in the 801 register.

Multi-jump register MJR3100 data is LR
It is set to AR220. In FIG. 9(a), LRA
Two bits of MJR3100 are set to bits 2 and 3 of R220, resulting in 4-way branching. (b
) shows an example of 16-way branching. As above, L
After the branch address is set in the RAR 220, the timing of the set signal is adjusted by the shift register 18o2, and the multi-jump control register 18o1 is reset. By doing this, the next time the jump address is set in the LRAR 220, the jump address from the microinstruction is set for all bits, and a normal unconditional branch can be performed.

Next, a method of stopping a microprogram by setting a breakpoint will be described as an effective means for debugging a microprogram.

A logic microprogram that describes a drawing algorithm requires a great deal of effort to debug due to the complexity of the description. Therefore, it is an effective means for debugging to stop the program at an arbitrary point while executing it and read the internal state. Figure 10 explains the method for stopping the microprogram in the above. be. Before running the program under test, breakpoint register (BPR) 1
Set the address you wish to stop in 60, run the program to be inspected, and LRAR 220 returns to BPR 160.
When they become the same, the -several output circuit outputs a matching signal. The coincidence signal is timed by shift register 1501 and sent to LRAR 220.

In the LRAR 220, an arbitrary address can be set by connecting the match signal to the set or reset terminal. FIG. 11 illustrates the above operation using a time chart.

The address set in this way is set as the start address of the fetch program of the next command.

In other words, internal information can be known by transferring a command to read internal registers after the program under test. After that, by sending a command that can be executed from any address, it is possible to re-execute the program to be inspected from the next address where it stopped.

FIG. 12 is an example of a graphic processing system to which the graphic processing device 10 according to the present invention is applied. central processing unit (CPU)
20 transfers commands and parameters from the system memory 30 to the graphic processing device i! Transfer to 10. Graphic processing device 10
interprets the command and executes drawing on the frame buffer 4o.

The figure drawn in this way is transferred to the display data converter 5.
0, it is converted into serial data and displayed on the display device 60.

〔Effect of the invention〕

According to the present invention, the microprogram that controls coordinate calculations and the microprogram that controls memory address calculations can be separated, so it is only necessary to write one graphic drawing algorithm in the microprogram that controls coordinate calculations. , it is possible to improve the program description and reduce the program capacity.

Another advantage of the present invention is that the number of multidirectional branches can be made variable, making it easier to write programs.

Another advantage of the present invention is that since the microprogram can be stopped at any address, the internal state at that time can be grasped, and efficient debugging can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the graphic processing device of the present invention, and FIG.
Figure 5 is a diagram showing details of the calculation section, Figure 6 is a diagram showing an example of two-level microprogramming, Figures 7 to 9 are diagrams showing details of multi-jump, and Figures 10 and 11 are breaks. FIG. 12, which is a diagram showing a method for stopping a microprogram by point setting, is a diagram showing an example of a graphic processing system to which the graphic processing device according to the present invention is applied. 10... Graphic processing device, 100... Physical micro program ROM, 140... WAIT control circuit,
150...-Several bases on base, 160... Break point register, 180... Multi-jump control circuit, 2
10...Logic microprogram ROM, 310...
Logical address calculation unit, 320...Physical address calculation unit, 330...Color data calculation unit.

Claims (1)

[Claims] 1. In a graphic processing device that controls the creation and transfer of graphic data to a display memory that stores graphic data, the first step is to sequentially calculate drawing coordinates according to a predetermined algorithm.
a second means for calculating a memory address corresponding to the drawing coordinates and executing drawing; a microprogram control device for controlling the first means; and a microprogram control device for controlling the second means. A graphic processing device, wherein: is separately provided, and the second microprogram is operated by a microprogram that controls the first means. 2. In the graphic processing device according to claim 1, the microprogram for controlling the second means is operated by the microprogram for controlling the first means, and then the program is operated independently. A graphic processing device characterized by the following features: 3. In the graphic processing apparatus according to claim 1, when the microprogram for controlling the first means operates the microprogram for controlling the second means, the second means is already controlled. 2. A graphics processing apparatus, characterized in that, when a microprogram that controls the first means is being executed, the microprogram that controls the first means is stopped until the execution is completed. 4. In the graphic processing device according to claim 1, third means for setting an address of a microprogram that controls the first means and information for branching the program in multiple directions are set. a fourth means for
and a fifth means for specifying a valid bit position of the means, and when the microprogram controlling the first means sets a jump address in the third means, the fifth means specifies the effective bit position of the means. 2. A graphics processing device, characterized in that multi-directional branching is possible by setting information of the fourth means in place of the jump address for the bit position of the jump address. 5. The graphic processing device according to claim 1, further comprising: a sixth means for setting an address for stopping a microprogram that controls the first means; A seventh means is provided for comparing the means and outputting a signal when they match, and the signal outputted by the seventh means is used as a set or reset signal for the third means, and when the matching signal is output, the A graphic processing device characterized in that unique data is stored in the third means.