JPS63219026A - Microcomputer - Google Patents

Abstract

PURPOSE:To speedily obtain a data as necessary, and besides, to reduce the load of a software by transferring and storing, like a hardware, the data, A/D- converted successively by an A/D converter, to and in a RAM at every machine cycle. CONSTITUTION:At first, at a time T1, a CPU1 reads out an instruction data from a ROM3 through an internal data bus 6, and stores it in the register of an inside. Next, the instruction data is decoded at the time T2 and T3. Now, because the internal data bus 5 is vacant at the time T2 and T3, the CPU1 outputs a control signal to the A/D converter 2 and the RAM3 at the time T2, and transfers the A/D-converted data from the converter 2 to the RAM3. At the time T5, the CPU1 reads in the data from the RAM3 through the bus 6 by a read operation, and at the time T6, it writes in the data in the RAM3 through the bus 6 by a write operation. In the next machine cycle as well, a similar processing is performed. Thus, the A/D-converted data is transferred from the converter 2 to the RAM3 at the time T2 and the latest data can be always obtained from the RAM3.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a microcomputer, and more specifically, to a microcomputer having a built-in A/D converter.

(B) Prior Art The operation of an A/D converter built into a conventional microcomputer can be started by a dedicated command from a CPU. Further, when the conversion operation of the A/D converter is completed, an interrupt is issued to the CPU, and the converted data is then transferred to the RAM in the microcomputer.

(c) Problems to be solved by the invention By the way, since the A/D conversion operation normally requires a time of 20 to 50 μsec, according to the conventional example, the CPU
The conversion data can only be obtained after the time required for the conversion has elapsed since the request.

Also, when the A/D conversion operation is completed, an interrupt is issued to the CPU, and if the interrupt is allowed, the A/D conversion data is transferred from the A/D converter to a specified RAM in the microcomputer, so the interrupt processing etc., the program becomes complicated.

The present invention was created in view of such conventional problems, and provides a microcomputer with a built-in A/D converter that makes it possible to obtain A/D converted data when necessary and reduces the burden on software. The purpose is to provide.

(=) Means for Solving the Problems The microcomputer of the present invention includes an A/D converter, a memory, and outputs a control signal to the A/D converter and memory at each specific microstate. By this, the A/D
The data converted by the converter is transferred to A via the internal bus.
It is characterized by having a CPU that transfers data from the /D converter to the memory one by one.

(e) The A/D conversion data converted by the action A/D converter is
Each time the internal bus is not used in a microstate, data is transferred from the A/D converter to the memory via the internal bus, and the latest A/D conversion data is stored in a specific storage area within the memory. .

Therefore, when the CPU needs A/D conversion data, it can read it from the memory in the same way as reading information from a normal memory, so it is fast.

Furthermore, since this is done without any program processing, the burden on the software is reduced.

(F) Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a microcomputer according to an embodiment of the present invention.

1 is a CPU; 2 is an A/D converter that converts input analog data into digital data; 3 is a RAM that stores the digital data; and 4 is a RAM that stores instructions to be processed by the CPU in a predetermined order. This is a ROM that has 5 is CPUI
This is a control signal that is output to the A/D converter 2 and RAM 3 at each specific microstate of the machine cycle, so that the digital data converted by the A/D converter 2 is output from the A/D converter 2. Transfer to RAM3 one by one. 6 is an internal data bus, CPUI.

Data can be mutually transferred between the A/D converter 2, RAM 3, and ROM 4 (7).

Next, the operation of the embodiment of the present invention will be explained with reference to the timing chart of FIG.

In addition, in the figure, φ1. -2 is a two-phase basic clock signal, and T1 to T6 are each microstate of the machine cycle.

First, the CPU transfers data from ROM3 to internal data bus 6 at T1.
The instruction data is read out via the CPU 1 and stored in the instruction register (IR) in the CPU 1 (instruction fetch). Next, the CPU decodes this instruction data at T2.73 (instruction decoding). By the way, at T2 and T3, the internal data bus 5 is empty, so the CPU
At 2:00, a control signal is output to the A/D converter 2 and RAM 3, and the A/D converted data is transferred from the A/D converter 2 to the RA.
Transfer to M3.

At 15:00, the CPU performs a read operation to read data from the RAM 3 via the internal data bus 6, and at 16:00, performs a write operation to read data from the RAM 3 via the internal data bus 6.
Write data to 3.

In the next machine cycle, the same processing as in the previous machine cycle is performed. As a result, the A/D converted data is transferred from the A/D converter 2 to the RAM 3 at 12 o'clock. As a result, the A/D conversion data in the RAM 3 is always the latest data.

As described above, according to the embodiment of the present invention, the data that has been A/D-converted by the A/D converter 2 is transferred to the RAM 3 in each machine cycle by hardware and stored in the RAM. Because the CPU is connected to A with almost no waiting time
/D conversion data can be obtained.

(G) As described in detail, according to the present invention, the CPU is equipped with the latest A/
Since D-converted data can be read from the RAM at any time, processing speed can be increased. Furthermore, since the transfer of A/D conversion data is performed by hardware, conventional interrupt processing and the like are not necessary, and the burden on software is reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a microcomputer according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation. 1...CPU, 2...A/D converter, 3...
・RAM, 4...ROM, 5...control signal,
6... Internal data bus. Applicant: Sanyo Electric Co., Ltd. and 1 other agent Patent attorney: Takuji Nishino and 1 other person Figure 1

Claims (1)

[Claims] An A/D converter, a memory, and a control signal converted by the A/D converter by outputting a control signal to the A/D converter and the memory at each specific microstate. 1. A microcomputer comprising a CPU that sequentially transfers data from an A/D converter to a memory via an internal bus.