JPS632152B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention is a silicon integrated MOSLSI that can improve noise resistance without reducing speed performance in highly integrated MOSLSI, especially standard cell type MOS logic LSI, gate array type MOS logic LSI, etc. This invention relates to a circuit device.

Conventionally, in memory LSIs and logic LSIs based on artwork design, the power supply (V _DD )
The area of the diffusion region connected to the terminal and ground (GND) terminal occupies a relatively large proportion of the total chip area, and this diffusion region contributes as junction capacitance, so the capacitance of the power supply and ground electrodes is large, and the noise characteristics are poor. It was in relatively good condition.

On the other hand, in recent years, automatic design of standard cell type and gate array type using CAD technology has progressed in logic LSI, especially custom and semi-custom LSI, and it has become possible to manufacture high-performance LSI in a short period of time. These types of LSIs have a cell area (region where standard cells and internal gate cells are placed)
It has a chip structure in which the wiring area and wiring area are clearly separated. That is, FIG. 1 is a plan view showing a part of a conventional logic LSI. In the same figure, 1 is the first Al for the signal line.
A wiring region where vertical and horizontal wiring such as an Al2 layer wiring layer between the wiring 2 and the second Al wiring 3 for signal line or an Al wiring layer and a polysilicon wiring layer are formed on a thick oxide film for the purpose of isolation between elements. , 4 is a cell region including a power supply (V _DD ) wiring 5, a ground (GND) wiring 6, a power supply diffusion region (shaded area at the bottom right) 7, and a diffusion region for ground (shaded area at the top right) 8.

In the following logic LSI with this configuration, the shaded area is the main capacitance between the power supply and the inside of the board and between the ground and the board. On the other hand, in the wiring region 1, the structure in which the wiring layer exists on a thick oxide film is necessary to reduce the stray capacitance accompanying the wiring and to increase the speed of the LSI. As LSIs become highly integrated, this wiring area 1 comes to occupy a large proportion of the total area of the chip, and for example, the wiring area 1 becomes two to three times as large as the cell area 4. Therefore, since the power diffusion region and the grounding diffusion region occupy only a further part of the cell area 4, the capacitance between the ground and the board and between the power supply and the board becomes a very small proportion when viewed from the whole chip. . This decreases the capacitance values of the power supply electrode and the ground electrode with respect to the substrate, deteriorating the noise resistance characteristics.

Note that this deterioration of noise resistance characteristics is caused by gate malfunction due to fluctuations in the power supply line and ground line caused by high-speed operation of internal driver gates and output buffer gates, and instability of the substrate potential when the substrate voltage (V _BB ) is internally generated. Due to ^the reduction in ^{operating margin} due to This means that damage to the power supply line due to the bipolar transistor turning on is more likely to occur.

Therefore, a method using gate capacitance has been proposed as a method of increasing the capacitance of the power supply and ground electrodes. This gate capacitance is determined by a thin oxide film (400 ~
1000 Å), and the capacitance value per unit area can be sufficiently large compared to junction capacitance, but it has the drawback of low reliability because it is vulnerable to destruction by noise.

Therefore, an object of the present invention is to effectively utilize the wiring area that occupies a large part of a chip, increase the capacitance of the power supply and ground electrodes without increasing the stray capacitance attached to the wiring layer, and improve the noise resistance. An object of the present invention is to provide a silicon integrated circuit device that can improve performance.

In order to achieve such an object, the present invention provides a silicon substrate and an insulating film that separates a device formed within the silicon substrate in a plane, supports a metal film for wiring inside a chip on the surface thereof, and an insulating film that supports a metal film for wiring inside a chip. An impurity region having a conductivity type opposite to that of the silicon substrate is formed on at least a part of a surface region of the substrate covered with a film, and this impurity region is connected to a power supply electrode or a ground electrode. This will be explained in detail using

FIG. 2 is a partial plan view of a chip showing an embodiment of the silicon integrated circuit device according to the present invention, and FIGS. 3 and 4 are a partially detailed plan view and vertical structure diagram thereof. As an example, standard cellular LSI
This shows the case where the test was carried out. In the same figure, 9 is the fourth
As shown in the figure, it is provided under a thick oxide film 10 (see FIG. 4) formed of a selective oxide film or an oxide film formed by CAD method, and connected to the power supply diffusion region 7 as shown in FIG. first embedded diffusion region, 1
1 is a selective oxide film or
Thick oxide film 10 formed by CVD method
A second buried diffusion region 12 is provided below (see FIG. 4) and connected to the grounding diffusion region 8, and an input/output buffer region 12 includes bonding pads and the like.

With this configuration, the first buried diffusion region 9 and the second buried diffusion region 11 cover almost the entire area of the chip, which contributes to the formation of junction capacitance and increases the capacitance between the power supply or ground power supply and the substrate. Therefore, noise characteristics can be improved.

In the vertical structure diagram of the silicon integrated circuit device shown in FIG. 4, 13 is a P ^- type semiconductor substrate;
4 is an isolation area. As shown in this figure, this capacitance type using a diffusion layer was applied to both the power supply and ground electrodes, but depending on the usage conditions of the LSI and other factors, the ratio of the capacitance to one of the electrodes was increased as follows. Of course, it may be implemented. First, LSIs that operate by applying a potential (backgate voltage) different from that of the ground electrode to the semiconductor substrate, especially LSIs that generate the backgate voltage on the chip, have to do with the operation speed and voltage of the LSI. In order to ensure a sufficient margin, it is necessary to reduce fluctuations in the back gate voltage. If the capacitance between the substrate and the ground electrode is increased, fluctuations in the back gate voltage can be reduced, so in this type of LSI, the area of the second buried diffusion region 11 grounded to the ground electrode and the area connected to the power supply electrode are reduced. It is desirable to increase the area of the first buried diffusion region 9 at the same time. In addition, in the case of an LSI that does not use a back gate voltage, that is, an LSI in which the potential of the semiconductor substrate and the ground electrode are the same, there is no need to increase the capacitance between the substrate and the ground electrode, and the first buried diffusion region connected to the power supply electrode is Maximize the area of 9,
Of course, the capacitance between the power supply and the board should be maximized.

Next, a method for manufacturing the silicon integrated circuit device shown in FIG. 2 will be explained with reference to the steps shown in FIGS. 5a to 5d. This manufacturing example shows a silicon gate, selective oxidation method, and N-channel MOS process. First, as shown in FIG. 5a, by photolithography, the nitride film 15 is left in the region where the thick oxide film 10 of the selective oxide film is to be formed, and P for isolation is formed on the protective oxide film 16 for ion implantation. Perform ion implantation of a type impurity (for example, boron ions).
Next, as shown in FIG. 5b, N-type impurity ions (for example, arsenic (As) ions) are implanted using a resist mask 17 in order to create a diffusion region that increases the capacitance of the power and ground electrodes. . This N
The concentration of the P-type impurity must be high enough to compensate for the P-type impurity for isolation. Next, as shown in FIG. 5c, selective oxidation is performed to form a thick oxide film 10 (for example, 1.2 to 1.5 μm) and to form a diffusion region. Normally, forming a selective oxide film requires a long heat treatment, so it is desirable to use an N-type impurity such as arsenic (As), which does not diffuse quickly even if the drive time is long.
Next, as shown in FIG. 5d, an ordinary selective oxidation process is performed to obtain a nearly completed structure. In addition, 18 is an overlying oxide film,
19 is gate polysilicon. Although the second aluminum wiring layer and passivation film are not shown, they are of course provided.

As explained in detail above, according to the silicon integrated circuit device according to the present invention, the wiring area that occupies a large part of the chip can be effectively utilized to increase the capacity of the power supply and/or ground electrode. This has the effect of improving noise resistance.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a part of a conventional logic LSI, FIG. 2 is a plan view of a part of a chip showing an embodiment of the silicon integrated circuit device according to the present invention, and FIGS. Partially detailed plan view and vertical structure diagram of the silicon integrated circuit device shown in Figure 2, Figure 5a
-FIG. 5d are cross-sectional views showing the method of manufacturing the silicon integrated circuit device shown in FIG. 2 in the order of steps. 1... Wiring area, 2... Al first wiring for signal line,
3...Al second wiring for signal line, 4...Cell area,
5...Power supply ( _VDD ) wiring, 6...Grounding (GND) wiring, 7...Diffusion region for power supply, 8...Diffusion region for grounding, 9...First buried diffusion region, 10...Thick oxide film , 11... second buried diffusion region, 12... input/output buffer region, 13... P ^- type semiconductor substrate,
14... Inlay region, 15... Nitride film, 16... Protective oxide film for ion implantation, 17...
Resist mask, 18...Top oxide film, 19...
...gate polysilicon. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A silicon substrate and an insulating film that separates a device formed within the silicon substrate in a plane and supports a metal film for wiring inside a chip on the surface thereof, and a silicon substrate covered with the insulating film. 1. A silicon integrated circuit device comprising: an impurity region having a conductivity type opposite to that of the silicon substrate formed on at least a part of a surface region of the silicon substrate, the impurity region being connected to a power supply electrode or a ground electrode. 2. The silicon integrated circuit device according to claim 1, wherein the impurity region is connected to either a power supply electrode or a ground electrode.