JPS63211765A - Vertical semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical semiconductor device for the purpose of switching or amplification and a method of manufacturing the same, and particularly relates to techniques for miniaturization and high performance.

(Prior art) Among MIS type semiconductor devices, MOS FEETs in particular were traditionally thought to be low voltage and low power devices, but with recent developments in semiconductor manufacturing technology and circuit design technology,
It has become possible to design high-voltage and high-power devices, and has now secured its place as a power device.

Typical examples of such high-voltage power MO5FETs include: ■offset gate structure, ■V-Groove or Ll-Groove structure, and ■DSA (Diffusi
On 5elf-8lignme-nt) structures are known, but among these, the conventional DSA structure power MO3FET (hereinafter referred to as O3A) is advantageous in terms of manufacturing technology and high performance.
FIG. 2(a) shows a plan view after electrode formation of M[]S) and a cross-sectional structure diagram taken along line A-A in this plan view.
and (b), and the cross-sectional structure in the next manufacturing process is shown in FIGS. 3(a) to (f). However, the source electrode is omitted in FIG. 2(a).

O8A MOS forms a channel by double diffusion, and the channel region is formed through the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon film 6 formed through a gate oxide film 5a. It is characterized by the impurity diffusion (into the p-type semiconductor M4) and the impurity diffusion (into the n+ type thick conductor layer 8) for forming the source region.In this case, the channel length is the same as that in the p-type semiconductor layer. The source electrode 9 formed on the insulating film 5d is a p-type semiconductor that forms the channel region of the n-type thick conductor layer 8 that forms the source region. Layer 4 (
Alternatively, it is in ohmic contact with both the p-type trench conductor layer 3. The gate electrode is generally shaped in a lattice shape or in a stripe shape, but the lattice shape is shown here. The n++ semiconductor substrate 1 is the drain region, and the n-on n-type semiconductor substrate 1 is the drain region, and the n-type epitaxial growth layer 2 is deposited thereon.
It has a structure. A drain electrode (not shown) is formed on the back surface of the chip, and when a positive voltage is applied between the gate and source to turn on the channel, current flows vertically from the substrate 1, passing through the channel region 4 and reaching the source region. Flows into 8. Note that the broken line in FIG. 2(a) indicates the outline of the opening in the polycrystalline silicon film pattern 6 constituting each cell.

Next, using FIGS. 3(a) to (f), we will explain the conventional O3AM
The manufacturing process of O3 will be explained. n゛゛n on the semiconductor substrate 1
The type epitaxial growth layer 2 has a specific resistance of 10 to 25, for example.
Ωam and a thickness of 30 to 60 μm, a p+ type groove conductor layer 3 is formed from the surface. Thereafter, a gate oxide film 5a was formed to a thickness of approximately 1000 wafers, as shown in FIG. 3(a).

Next, a polycrystalline silicon film 6 is deposited to a thickness of, for example, 6000 nm, and then selectively patterned, and ions are implanted using this polycrystalline silicon film pattern as a mask to form a p-type semiconductor layer 4 that will become a channel region. Form in a self-consistent manner. This situation is shown in FIG. 3(b).

Next, using photoresist by photo-etching technique, openings were selectively formed in the areas where the n-type trench conductor layer 8, which will become the source region, was to be formed, as shown in FIG. 3(C).

Next, an n+ type semiconductor layer 8 and an oxide film 5b, which will become a source region, are formed (as shown in FIG. 3(d)), and then CVD
PSG (Phospho 5ilinate G)
FIG. 3(e) shows how the film 5C (lass) was deposited to a thickness of about 8,000 mm. In FIG. 2(b), this oxide film 5
b and the PSG film 5C are shown together as a second insulating film 5d.

Next, after performing various heat treatments, the oxide film 5b and the PSG
By forming an electrode extraction opening 10a in the film 5C and forming an aluminum (i) electrode 9, the source-drain breakdown voltage V is increased. 8. is around 200 to 600v in the USA
MOS FBT is completed. This situation is shown in FIG. 3(f).

In general, MOS FBTs have the advantage of being able to perform high-speed switching because there is no accumulation of minority carriers, and are highly thermally stable because their drain current has a negative temperature coefficient. Compared to a type transistor, since it is a majority carrier element, there is a significant trade-off between high withstand voltage and high power.The substrate resistance layer required for high withstand voltage directly leads to an increase in saturation voltage, and the on-resistance increases with the same chip area. It had the disadvantage of being large. In order to solve this problem, it is necessary to reduce the resistance of the power path of the FBT, especially the drain resistance.

In other words, the question is how to increase drain interviewing efficiency, and for this purpose, it is necessary to design the best pattern by making full use of microfabrication technology. A DSA MOS FET is generally employed as a structure that satisfies these requirements.

(Problems to be Solved by the Invention) However, the structure of the conventional DSA MOS FBT is not necessarily optimal. Various measures must be taken regarding the polycrystalline silicon film pattern and the shape of the channel region so that the width of the current path, that is, the channel width, which is the peripheral length of the channel, can be increased within the limited area of the silicon chip. By increasing the channel width, it is possible to increase the drain current and also obtain a large mutual conductance g in the large current region.

Since these are the biggest factors that make it possible to reduce on-resistance, the biggest goal was how to increase the channel width within a limited area.

However, if the area of the channel region is increased in order to increase the channel width in a conventional structure, the chip size increases, which inevitably leads to a reduction in yield. Therefore, in recent technology,
Methods are being used to lengthen the channel width by making full use of microfabrication technology. However, as the pattern becomes finer, shallower diffusion becomes necessary, resulting in the formation of a thin and long source region pattern, which has the drawback of increasing its resistance value and even increasing the on-resistance. Ta.

In the conventional DSA MOS FET mentioned above, the channel region and the source region are formed by double diffusion, so the channel region has an impurity concentration gradient when viewed in the direction along the surface, and as a result, the diffusion of the source region is The gate threshold voltage will vary due to the non-uniformity of the depth. For this reason, the channel region is made deep, for example, 4 to 5 μm, and the source region is formed shallow, 1 μm, so as not to be affected by the concentration gradient. However, with this deep channel region, the transconductance g.

The on-resistance could not be lowered due to the smaller on-resistance, and as a result, the switching speed could not be increased.

In order to eliminate such drawbacks, the present inventors disclosed
As described in Japanese Patent Nos. 1-158180 and 61-158181, it has been proposed to form a channel region by implanting impurity ions.

For example, in Japanese Patent Application Laid-Open No. 61-158180, an insulating film is formed in an overhang shape on a gate polycrystalline silicon pattern, ions are implanted to form a channel region through this insulating film, and a source region is formed. Ion implantation for this purpose is performed using an insulating film as a mask to form a shallow channel region with a uniform impurity concentration. Furthermore, in Japanese Patent Application Laid-Open No. 61-158181, a mask is selectively formed on a gate polycrystalline silicon pattern to perform ion implantation for forming a channel region, and then a source is implanted using the gate polycrystalline silicon pattern as a mask. Ion implantation for region formation is performed to form a shallow channel region with uniform impurity concentration.

However, in these methods, since the gate polycrystalline silicon pattern acts as a mask for ion implantation, this gate polycrystalline silicon pattern cannot be extended above the source region, and the gate polycrystalline silicon pattern must be formed on the surface of the epitaxial layer via a thin gate oxide film. On the other hand, electric field concentration tends to occur at the edges of the gate polycrystalline silicon pattern, which can destroy the thin gate oxide film, cause a short circuit between the gate and source, and cause current to flow at a gate voltage lower than the gate threshold voltage. There is a drawback that such a situation occurs.

The present invention has been made in view of the above-mentioned points, and it eliminates the impurity concentration gradient in the channel region to stabilize the gate threshold voltage, and also provides a thick insulating film near the edge of the gate polycrystalline silicon pattern. Furthermore, by providing a polycrystalline silicon pattern on the source region, the surface concentration of the source region can be increased, and as a result, the on-resistance can be lowered. It is an object of the present invention to provide a vertical semiconductor device and a method for manufacturing the same, in which the pattern can be made finer by using a crystalline silicon pattern for wiring, and the channel width can be increased to further lower the on-resistance.

(Means for solving the problem) The vertical semiconductor device of the present invention includes a semiconductor substrate of one conductivity type,
A first semiconductor region of opposite conductivity type formed on the surface of this semiconductor substrate, a second semiconductor region of one conductivity type formed within this first semiconductor region, and a second semiconductor region of one conductivity type formed on this second semiconductor region. In addition, a polycrystalline semiconductor film pattern containing a large amount of impurities of one conductivity type, a first insulating film formed on the surface of the semiconductor substrate, and at least the first and second insulating films formed on the first insulating film. a second conductor pattern made of a semiconductor film or a conductor film formed so as to partially overlap the semiconductor region; a second insulating film formed on the second conductor pattern; and a second insulating film. The device is characterized in that it further includes a metal electrode film formed to be connected to the polycrystalline semiconductor pattern.

Further, the method for manufacturing a vertical semiconductor device according to the present invention includes a first semiconductor region of an opposite conductivity type formed on the surface of a semiconductor substrate of one conductivity type, and a first semiconductor region of one conductivity type formed inside the semiconductor region of the opposite conductivity type. a second semiconductor region; a first insulating film formed on the surface of the semiconductor substrate so as to partially overlap with the first right and second semiconductor regions; and a first insulating film formed on the first insulating film. and a second conductor pattern formed on the second semiconductor region, forming a polycrystalline semiconductor film on the surface of the semiconductor substrate of one conductivity type. a step of selectively oxidizing this polycrystalline semiconductor film to form a thick oxide film on the semiconductor substrate, and ion-implanting an impurity of the opposite conductivity type into the polycrystalline semiconductor using the thick oxide film as a mask. A step of performing heat treatment to diffusely form the first semiconductor region on the surface of the semiconductor substrate, and implanting an impurity of one conductivity type into the polycrystalline semiconductor film using the thick oxide film as a mask, and then performing heat treatment to form the first semiconductor region. After forming a second semiconductor region in the semiconductor region and transforming the polycrystalline semiconductor film into the second conductor pattern, and removing the thick oxide film by etching, the surface of the semiconductor substrate and the surface of the polycrystalline semiconductor film are removed. forming the first insulating film on the first insulating film; forming the first conductor pattern on the first insulating film; forming a second insulating film on the first conductor pattern; The method is characterized by comprising a step of forming a metal electrode film on the second insulating film so as to be connected to the second conductor pattern made of the polycrystalline semiconductor film.

(Function) In the vertical semiconductor device of the present invention described above, the second semiconductor region of one conductivity type constituting the source or drain region is formed by diffusion from a polycrystalline semiconductor film containing a large amount of impurities of one conductivity type. Therefore, the surface concentration of the second semiconductor region can be increased, and the second semiconductor region can be formed shallowly and uniformly, so that the on-resistance can be reduced. Furthermore, since this polycrystalline semiconductor film can be used for wiring, it is possible to miniaturize the pattern, and the channel width can be further shortened, which also leads to a reduction in on-resistance.

Furthermore, since the second conductor pattern constituting the gate electrode pattern is located on the polycrystalline semiconductor film pattern via the thick first insulating film, there is no dielectric breakdown even if electric field concentration occurs at the edge of the gate electrode pattern. This eliminates the fear that this may occur.

(Embodiment) FIGS. 1(a) to Q'1) are cross-sectional views showing the structure of an embodiment of a vertical semiconductor device according to the present invention in successive manufacturing steps.

First, as shown in FIG. 1(a), for example, a 1 to 2 Ω-
n-type silicon epitaxial layer 1 with a resistivity of cm
2 is formed to have a thickness of, for example, 10 to 12 μm. next,
A p-type half layer 13 is formed on the surface of this n-type epitaxial layer 12 to a depth of, for example, 4 to 5 μm.

Next, a polycrystalline silicon film 14 that does not contain impurities is deposited on the surface of the n-type epitaxial layer 12 to a thickness of about 5000 nm, and then, for example, a polycrystalline silicon film 14 of 200 to 500 nm or 1000 to 2000 nm thick is deposited on the surface of the n-type epitaxial layer 12. After forming the oxide film 15, an oxidation-resistant insulating film 16 made of, for example, Si3N is formed to a thickness of, for example, about 1,000 mm, as shown in FIG. 1(b).
Shown below.

Next, after selectively etching the oxidation-resistant insulating film 16,
Using this as a mask, the polycrystalline silicon film 14 was selectively oxidized to form a thick oxide film 17 of about 1.2 μm, as shown in FIG. 1C.

Next, after removing the oxidation-resistant insulating film 16 made of Si and N4 by dry etching using hot phosphoric acid or Freon, p-type impurities are etched using the thick oxide film 17 selectively formed as described above as a mask. For example, boron ions are implanted into the polycrystalline silicon film 14. Thereafter, a heat treatment is performed to diffuse the ion-implanted impurities to transform the polycrystalline silicon film 14 into p-type, and to form a p-type semiconductor region 18 on the surface of the epitaxial layer 12 underneath. This situation is shown in FIG. 1(d).

Next, using the thick oxide film 17 as a mask, a large amount of n-type impurity is ion-implanted into the p-type child crystal silicon film 14, and then heat treatment is performed to transform the p-type child crystal silicon film into an n-type and to make it a p-type semiconductor. FIG. 1(e) shows how the n+ type semiconductor region is diffused and formed inside the region 18.

Next, after removing the thick oxide film 17 by etching,
For example, FIG. 1(f) shows how 500 to 1000 gate insulating oxide films 20 are formed. This gate oxide film 2
0 is formed by thermal oxidation, but in this case, the thickness of the oxide film formed on the n-type polycrystalline silicon film 14 is equal to that of the oxide film formed on the surface of the epitaxial layer 12, which is single crystal silicon. It becomes thicker than the film thickness (about twice as much). In order to further increase the thickness of the oxide film on the polycrystalline silicon film,
It is also possible to first perform wet oxidation, then perform etching until the oxide film on the epitaxial layer disappears, and then perform thermal oxidation to form a gate oxide film. This method is even better because the thickness of the oxide film formed on the polycrystalline silicon film by wet oxidation is about ten times that of the oxide film formed on the epitaxial layer.

Next, on the gate oxide film 20, a gate conductor pattern 21 made of an n-type packed crystalline silicon film is formed to a thickness of approximately 5000 nm so as to partially overlap the n-type polycrystalline silicon film 14. The situation is shown in Fig. 1(g).

This gate conductor pattern 21 can also be formed of a p1 type polycrystalline silicon film or a high melting point metal film.

Finally, CVD-3iO is placed on the gate conductor pattern 21.
After forming the insulating film 22 made of □ or CVD-PSG film, a contact hole for the n-type polycrystalline silicon film 14 was formed, and a metal electrode film 23 made of aluminum was formed thereon to a thickness of about 3 μm. The situation is shown in Figure 1 (Sha). Further, by depositing a metal electrode film acting as a drain electrode on the back surface of the n+ type semiconductor substrate 11, a MOS PET with a withstand voltage of about 60V is completed.

The present invention is not limited to the embodiments described above, but can be modified and modified in many ways. For example, in the above-described embodiment, the gate electrode material is polycrystalline silicon, but is not limited to this, and may include Mo, Ni, etc.

It can also be a high melting point metal such as Cr or Ti, or a high melting point metal compound such as molybdenum silicide, nickel silicide, or platinum silicide. Further, the p conductivity type and the n conductivity type may be opposite. Further, in the embodiments described above, the source region is formed on the surface of the epitaxial layer and the n-type substrate is used as the drain region, but this relationship can also be reversed. Further, in the above-described embodiments, the p' type semiconductor layer was formed integrally with the p type semiconductor layer constituting the channel region, but this p' type semiconductor layer is not necessarily necessary.

(Effect of the invention) The effects of the present invention described above are summarized as follows.

(1) Since the n + -type semiconductor region constituting the source or drain region can be formed by diffusion from polycrystalline silicon containing a large amount of n-type impurities, a shallow diffusion layer with extremely good controllability can be formed. Therefore, the source or drain region can be made to have any high concentration depending on the purpose.
It is possible to prevent an increase in on-resistance due to an increase in ohmic contact resistance. Additionally, as a result, the pattern width of the source or drain region can be reduced.
This enables miniaturization and allows the channel width to be made longer.

(2) Since the gate conductor pattern exists on the polycrystalline semiconductor film that constitutes the source or drain conductor pattern via a thick oxide film, it effectively prevents gate breakdown voltage from deteriorating due to electric field concentration at the edges of the gate conductor pattern. can do.

(3) The polycrystalline semiconductor film on the source or drain region can be used as a conductive pattern for wiring.
It becomes possible to miniaturize the baton, making it possible to further increase the channel width, thereby making it possible to further suppress the on-resistance.

[Brief explanation of the drawing]

FIGS. 1(a) to (5) are cross-sectional views showing the configuration of an embodiment of the vertical semiconductor device according to the present invention in sequential manufacturing steps, and FIGS. 2(a) and (b) are cross-sectional views of the conventional vertical semiconductor device. A plan view and a sectional view showing the structure. FIGS. 3(a) to 3(f) are sectional views showing the structure of a conventional vertical semiconductor device in successive manufacturing steps. 11... n-type silicon substrate 12... n-type epitaxial layer 13... p-type semiconductor layer 14... polycrystalline silicon film 15... oxide film 16... oxidation-resistant insulating film 17 ...Thick oxide film 18...P type semiconductor region 19...N゛ type semiconductor region 20...Gate oxide film 21...Gate conductor pattern 22...Insulating film 23...Metal electrode film Patent applicant: TDC Co., Ltd. Figure 1 Figure 3 (a) Figure 3 (d) (e) Figure 3 (f)

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a first semiconductor region of an opposite conductivity type formed on the surface of this semiconductor substrate, and a semiconductor substrate of one conductivity type formed in this first semiconductor region. a second semiconductor region; a polycrystalline semiconductor film pattern containing a large amount of one conductivity type impurity formed on the second semiconductor region; a first insulating film formed on the surface of the semiconductor substrate; a second conductor pattern made of a semiconductor film or a conductor film formed on the first insulating film so as to overlap at least partially with the first and second semiconductor regions; and on the second conductor pattern. A vertical semiconductor device comprising: a second insulating film formed on the second insulating film; and a metal electrode film formed on the second insulating film so as to be connected to the polycrystalline semiconductor pattern. 2. A first semiconductor region of an opposite conductivity type formed on the surface of a semiconductor substrate of one conductivity type, a second semiconductor region of one conductivity type formed inside the semiconductor region of the opposite conductivity type, and the semiconductor substrate a first insulating film formed on the surface of the semiconductor region so as to partially overlap with the first and second semiconductor regions; a first conductor pattern formed on the first insulating film; and a first conductor pattern formed on the second semiconductor region. a step of forming a polycrystalline semiconductor film on the surface of the semiconductor substrate of one conductivity type; A step of oxidizing to form a thick oxide film on the semiconductor substrate, and ion implantation of an impurity of the opposite conductivity type into the polycrystalline semiconductor using the thick oxide film as a mask, followed by heat treatment to form a thick oxide film on the surface of the semiconductor substrate. a step of diffusing and forming a semiconductor region, and implanting an impurity of one conductivity type into the polycrystalline semiconductor film using the thick oxide film as a mask, and then performing heat treatment to form the first semiconductor region.
forming a second semiconductor region in the semiconductor region and transforming the polycrystalline semiconductor film into the second conductor pattern;
After removing the thick oxide film by etching, forming the first insulating film on the surface of the semiconductor substrate and the surface of the polycrystalline semiconductor film, and forming the first conductor pattern on the first insulating film. forming a second insulating film on the first conductive pattern; and forming a metal electrode film on the second insulating film so as to be connected to the second conductive pattern made of the polycrystalline semiconductor film. 1. A method for manufacturing a vertical semiconductor device, comprising the step of forming a vertical semiconductor device.