JPS63211652A - Package for integrated circuit - Google Patents
Package for integrated circuitInfo
- Publication number
- JPS63211652A JPS63211652A JP62044295A JP4429587A JPS63211652A JP S63211652 A JPS63211652 A JP S63211652A JP 62044295 A JP62044295 A JP 62044295A JP 4429587 A JP4429587 A JP 4429587A JP S63211652 A JPS63211652 A JP S63211652A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- case
- integrated circuit
- sides
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明１塩集積回路素子を搭載したパッケージケース裏
面にはんだ付は用の電極が引出されていて、プリント基
板の導体面に直接はんだ付けで実装されるリードレスチ
ップキャリア型の集積回路パッケージに関する。[Detailed Description of the Invention] [Field of Industrial Application] Invention 1: A soldering electrode is drawn out on the back of the package case in which the integrated circuit element is mounted, so that it can be soldered directly to the conductor surface of the printed circuit board. The present invention relates to a leadless chip carrier type integrated circuit package to be mounted.
第４図（ａ）は従来のこの種のパッケージに集積回路素
子（以下ＩＣチップという）ｔ−搭載したキャップなし
の状態を示す平面図、同図（ｂ）は同図（ａ）のＡ−Ａ
断面図、同図（ｃ）は同図（ａ）の１３−ｉ３断面図で
ある。第２図（ａ）において、パッケージケース１１の
中央凹所にＩＣチップ１０が固着され、チップ１０のパ
ッド部とケース１１の内部リード２との間はボンディン
グ線３で接続されている。ケース１１の周辺には側壁４
があり、この側壁４の上面のキャップとの封止面６は、
第４図（ｂ）に見られるように、山なりに曲げられてい
るボンディング線３の最高到達点より高い位置にあシ、
キャップをかぶせて封止する場合、キャップの下面が、
ボンティング線３に接触しないようになっている。FIG. 4(a) is a plan view showing a state in which an integrated circuit element (hereinafter referred to as an IC chip) is mounted on a conventional package of this type without a cap, and FIG. A
A sectional view of the same figure (c) is a 13-i3 sectional view of the same figure (a). In FIG. 2(a), an IC chip 10 is fixed in a central recess of a package case 11, and a bonding wire 3 is connected between a pad portion of the chip 10 and an internal lead 2 of the case 11. There is a side wall 4 around the case 11.
The sealing surface 6 with the cap on the upper surface of the side wall 4 is
As seen in Figure 4(b), there is a reed at a position higher than the highest point of the bonding wire 3, which is bent into a mountain shape.
When sealing with a cap, the bottom surface of the cap
It is designed not to come into contact with the bonding wire 3.
近年、ＩＣは高速動作で多機能化が要求される様になっ
てきている為、チップも大きくなシつつある。それに対
しパッケージは高密度実装が要求される為、できるだけ
小さくしなければならないという問題が生じてきて・い
る。しかしながら、上述した従来のパッケージは、ボン
ディング時の制約等からパッケージにとり載することが
できるチ、プサイズはかなり制限を受ける。すなわち、
第５図はパッケージにＩＣチップをとり載した後、アル
ミニウム線を超音波ボンディングしている時の断面図を
示したものであり、第５図において、パッケージケース
１１の側壁４の高さｈに対し、キャップをかぶせてふた
をし封止した時に、ボンディング装置のボンディングヘ
ッド１２によりボンディングされるボンディング線３に
接触しない様にボンディング＃３の最高到達点の高さＨ
に対して、
ｈ＞ｎ
の関係がある。一方とう載できるチップサイズに大きな
影！＃をあたえるパッケージケース１１の内部リード２
のリード長Ａは、ボンディング装置のポンディングヘッ
ド１２によシボンディングされるボンティング線３が側
壁４に引かからないためには下記に示す以上の長さが必
要となる。In recent years, ICs have been required to operate at high speed and have multiple functions, so chips are also becoming larger. On the other hand, since packages require high-density packaging, the problem has arisen that they must be made as small as possible. However, in the conventional package described above, the size of chips that can be mounted on the package is considerably limited due to constraints during bonding and the like. That is,
FIG. 5 shows a cross-sectional view of the aluminum wire being ultrasonically bonded after the IC chip is mounted on the package. On the other hand, when the cap is put on and the lid is sealed, the height H of the highest point of bonding #3 is set so that it does not come into contact with the bonding wire 3 bonded by the bonding head 12 of the bonding device.
There is a relationship h>n. On the other hand, there is a big problem with the chip size that can be loaded on the ship. Internal lead 2 of package case 11 that gives #
The lead length A needs to be longer than the length shown below in order to prevent the bonding wire 3 that is bonded by the bonding head 12 of the bonding device from being pulled onto the side wall 4.
Ａ）ｈ・□ θ：ボンディング線の角ｔａｎ θ
例えば、θ＝３０°、ｈ＝３０（１ｍの場合、人は５２
０μｍ以上必要である。しかし実際には、ボンティング
時の位置的バラツキ、リード部に使用されているＡｕパ
ターンのズレ等を考慮してさらに余分の長さを必要とす
る。もち論、この内部リード長Ａが短かければ、一定の
大きさのパッケージに対し、より大きなＩＣチップを搭
載できるわけであるから、成る可く短くできることが望
まれる。A) h・□ θ: Angle tan θ of the bonding line For example, θ=30°, h=30 (in the case of 1 m, a person is 52
It is necessary to have a thickness of 0 μm or more. However, in reality, an extra length is required in consideration of positional variations during bonding, misalignment of the Au pattern used in the lead portion, and the like. Of course, if the internal lead length A is short, a larger IC chip can be mounted on a package of a certain size, so it is desirable to make it as short as possible.
本発明の集積回路パッケージは、集積回路素子ｔとう叔
するリードレスチップキャリア型の集積回路パッケージ
であって、パッケージケースの封止用キャップとの４辺
の縁辺にある封止面のうち、対向する一対の２辺の縁辺
にある封止面が、ケースに搭載するＩＣチップのパッド
部とケース周辺の内部リードとの間を接続するボンディ
ング線の高さ方向の最高到達点より低くし、他の一対の
対向する２辺の縁辺の封止面を高くしている。The integrated circuit package of the present invention is a leadless chip carrier type integrated circuit package in which an integrated circuit element t is inserted. The sealing surfaces on the edges of the pair of two sides are lower than the highest point in the height direction of the bonding wire that connects the pad part of the IC chip mounted on the case and the internal leads around the case, and The sealing surfaces of the pair of two opposing edges are raised.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第１図（ａ）は本発明の一実施例のキャップなしの平面
図、同図（ｂ）は同図（ａ）のＡ−Ａ断面図、同図（Ｃ
）は同図（ａ）の゛Ｂ−８断面図である。これらの図に
おいて、パッケージケースｌの中央凹所に集積回路チッ
プ１０が固着され、チップ１０の周辺のパッド部とこの
パッドに対応して設けられたケースｌの周辺の台上に設
けられている内部リード２との間は山なりに曲けられた
ボンティング線３により接続されている。長方形のケー
ス１の相対向する短辺の縁部には、ボンディング線３の
最高到達点の高さより高い側壁４が設けられている。一
方、ケース１の対向する長辺の縁部にはチップ１０のバ
ッド面と同じ高さの内部リード形成台部そのままである
。したがって、内部リード形成台部の幅のうち、キャッ
プとの封止面６０幅を除いたチップ１の長辺側の内部リ
ード長Ａは、リード長を長くする側壁がないので、ボン
ディングに必要な最知の長さで早足シるため、短くなっ
ている。よってその分だけ、従来のパッケージの横幅よ
り小さくできる。換言すれば、同じ大きさのパッケージ
なら、横幅の大きい集積回路チップが搭載できることに
なる。FIG. 1(a) is a plan view of an embodiment of the present invention without a cap, FIG. 1(b) is a sectional view taken along line A-A in FIG. 1(a), and FIG.
) is a sectional view taken along line B-8 in FIG. In these figures, an integrated circuit chip 10 is fixed in the central recess of a package case l, and is provided on a pad around the chip 10 and a stand around the case l provided corresponding to the pad. It is connected to the internal lead 2 by a bonding wire 3 bent into a mountain shape. A side wall 4 higher than the height of the highest point of the bonding line 3 is provided at the edges of opposite short sides of the rectangular case 1. On the other hand, on the opposing long edges of the case 1, there is an internal lead forming pedestal at the same height as the pad surface of the chip 10. Therefore, the internal lead length A on the long side of the chip 1 excluding the width of the sealing surface 60 with the cap out of the width of the internal lead forming base is the same as that required for bonding since there is no side wall that increases the lead length. It is short because it is a quick walk at the best length. Therefore, the width can be made smaller than the conventional package by that much. In other words, a package of the same size can accommodate a wider integrated circuit chip.
第２図は第１図の実施例に適合するキャップ８のｓｉｎ
図である。キャップ８は、従来の千叛形のキャップと異
な９、長辺側の縁部には、ケース１の側壁のない台部の
封止代と接触封止するために、短辺縁部の側壁４と同じ
高さの突出ふち８ａが形成されている。FIG. 2 shows the sin of the cap 8 adapted to the embodiment of FIG.
It is a diagram. The cap 8 is different from the conventional 100%-shaped cap 9. The long edge of the cap 8 has a side wall of the short edge for contact sealing with the sealing margin of the pedestal without side walls of the case 1. A protruding edge 8a having the same height as 4 is formed.
第３図は本発明の第２の実施例のパッケージケースにｌ
Ｃチップを搭載したのち、アルミのボンディング線３を
超音波ボンディングしている状態を示す部分断面図であ
る。図において、これを第１図の実施例と比べた場合、
ケース７の長辺側の縁部にはボンディング線３の最高到
達点の高さより充分低い側壁５を有することが異なって
いる。Figure 3 shows the package case of the second embodiment of the present invention.
FIG. 3 is a partial cross-sectional view showing a state in which aluminum bonding wires 3 are ultrasonically bonded after a C chip is mounted. In the figure, when comparing this with the embodiment shown in Figure 1,
The difference is that the long side edge of the case 7 has a side wall 5 that is sufficiently lower than the height of the highest point of the bonding line 3.
本例では、側壁５があっても、その高さが低いので、ボ
ンディング装置のボンディングヘッド１２と側壁５とは
十分近付けるので、内部リード長Ａは従来のものに比べ
て短くでき、その分パッケージの横幅金小さくできる。In this example, even if there is a side wall 5, its height is low, so the bonding head 12 of the bonding device and the side wall 5 can be brought close enough to each other, so the internal lead length A can be shortened compared to the conventional one, and the package can be packaged accordingly. The width can be made smaller.
なお上側は、長方形のパッケージの四つ縁辺のうちの対
向する２つの長辺側の側壁ヲ低くしているが、長辺側は
従来通り高くして、短辺側を低くすることもできるのは
いうまでもない。In addition, on the top side, the side walls on the two opposing long sides of the four edges of the rectangular package are lowered, but it is also possible to make the long sides higher as before and lower the short sides. Needless to say.
本発明によれば、ボンティング時の制約を受けないため
、内部リード長を短かくすることができる。従がって、
従来パッケージに比べて大きなチップサイズまでとう載
できる効果がある。また、ボンディング線の最高到達点
より低い封止面が２方向の為、ＩＣチップのとり載から
封止までの間に不慮の事故（裏返し等）があってもボン
ディング線への影響は、従来品と同等である。According to the present invention, since there are no restrictions during bonding, the internal lead length can be shortened. Accordingly,
Compared to conventional packages, it has the effect of allowing larger chip sizes to be mounted. In addition, since the sealing surfaces that are lower than the highest point of the bonding wire are in two directions, even if an unexpected accident (such as turning the IC chip over) occurs between mounting the IC chip and sealing, the bonding wire will not be affected. It is equivalent to the product.
第１図（ａ）は本発明の一実施例にＩＣチップを搭載し
たキャップなしの平面図、同図（ｂ）は同図（ａ）のＡ
−Ａ断面図、同図（Ｃ）は同図（ａ）のＢ−Ｂ断面図、
第２図は第１図の実施例に伺属するキャップの斜視図、
第３図は本発明の他の実施例にＩＣチップを搭載後のホ
ンディング線のボンディングを示す部分断面図、第４図
（ａ） 、 （ｂ） 、 （ｃ）は第１図の実施例に対
応する従来例の平面図、およびそのＡ−ＡならびにＢ−
Ｂ断面図、第５図は従来のボンティング線ポンディング
時の内部リード長と側壁の高さの関係全説明するだめの
断面図である。
１．７．１１・・・・・・パッケージケース、２・・・
・・・内部リード、３°°゛°・°ボンディング線、４
・・・・・・高い側壁、５・・・・・・低い側壁、６・
・・・・・封止面、８・・・・・・キャップ、８ａパ°
・・・突出ふち、１０・・・・・・１Ｃチツプ、１２・
・・・・・ボンディングヘッド。
代理人 弁理士 内 原 ！ 、９゛、、て、Ｘ
、？１翁 １図
第２図
躬 ５図FIG. 1(a) is a plan view of an embodiment of the present invention with an IC chip mounted thereon without a cap, and FIG. 1(b) is an A of FIG. 1(a).
-A sectional view, the same figure (C) is the BB sectional view of the same figure (a),
FIG. 2 is a perspective view of a cap that corresponds to the embodiment shown in FIG. 1;
FIG. 3 is a partial cross-sectional view showing the bonding of the bonding wire after mounting an IC chip on another embodiment of the present invention, and FIGS. 4(a), (b), and (c) are the embodiment of FIG. 1. A plan view of the conventional example corresponding to , and its A-A and B-
B sectional view, FIG. 5 is a sectional view for explaining the entire relationship between internal lead length and side wall height during conventional bonding wire bonding. 1.7.11...Package case, 2...
...Internal lead, 3°°゛°・°bonding wire, 4
...High side wall, 5...Low side wall, 6.
...Sealing surface, 8...Cap, 8a pa°
...Protruding edge, 10...1C tip, 12.
...Bonding head. Agent Patent Attorney Uchihara! ,9゛,,te,X
,? 1. Figure 1. Figure 2. Figure 5.
Claims (1)
し封止するキャップとを有するリードレスチップキャリ
ア型の集積回路パッケージにおいて、前記ケース４辺の
うちの一対の対向する２辺の縁辺の前記キャップとの封
止面が、前記搭載した集積回路素子のパッド部と前記ケ
ース周辺に形成された内部リードとの間を接続するボン
ディング線の最高到達点に対し高い位置にあり、他の一
対の対向する２辺の縁辺の封止面が低い位置にあること
を特徴とする集積回路パッケージ。In a leadless chip carrier type integrated circuit package that has a case in which an integrated circuit element is mounted and a cap that covers and seals the case, the The sealing surface with the cap is located at a higher position than the highest point of the bonding wire connecting between the pad part of the mounted integrated circuit element and the internal lead formed around the case, and An integrated circuit package characterized in that the sealing surfaces of two opposing edges are located at a low position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62044295A JP2521944B2 (en) | 1987-02-26 | 1987-02-26 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62044295A JP2521944B2 (en) | 1987-02-26 | 1987-02-26 | Integrated circuit package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63211652A true JPS63211652A (en) | 1988-09-02 |
| JP2521944B2 JP2521944B2 (en) | 1996-08-07 |
Family
ID=12687517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62044295A Expired - Lifetime JP2521944B2 (en) | 1987-02-26 | 1987-02-26 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2521944B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH056984A (en) * | 1991-06-27 | 1993-01-14 | Nec Corp | One-dimensional image sensor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11600687B2 (en) | 2020-03-13 | 2023-03-07 | Samsung Display Co., Ltd. | Electronic device package and display device including the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6247135U (en) * | 1985-09-10 | 1987-03-23 |
-
1987
- 1987-02-26 JP JP62044295A patent/JP2521944B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6247135U (en) * | 1985-09-10 | 1987-03-23 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH056984A (en) * | 1991-06-27 | 1993-01-14 | Nec Corp | One-dimensional image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2521944B2 (en) | 1996-08-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100214561B1 (en) | Rip Lead Package | |
| US6882056B2 (en) | Multi-chip package type semiconductor device | |
| KR100328906B1 (en) | Method and device for joining leads inside lead-on chip of leadframe | |
| JP2004071947A (en) | Semiconductor device | |
| JP2885414B2 (en) | Semiconductor device, mounting method thereof, and electronic device | |
| US6791166B1 (en) | Stackable lead frame package using exposed internal lead traces | |
| JP2873953B2 (en) | Bottom lead type semiconductor package | |
| JPS58219757A (en) | Semiconductor device | |
| JPS63211652A (en) | Package for integrated circuit | |
| JP3917344B2 (en) | Semiconductor device and method for mounting semiconductor device | |
| JPH01137660A (en) | semiconductor equipment | |
| EP0036907B1 (en) | Multi-lead plug-in type package for circuit element | |
| JP3174238B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP2885786B1 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JPH01220837A (en) | Semiconductor integrated circuit device | |
| JP2913858B2 (en) | Hybrid integrated circuit | |
| JPH03163858A (en) | Resin-sealed semiconductor device | |
| KR0161620B1 (en) | Ceramic package having a centerpad type semiconductor chip | |
| KR940010298A (en) | Semiconductor package and manufacturing method thereof | |
| JPH0287635A (en) | Ceramic package semiconductor device | |
| JPH06268152A (en) | Semiconductor integrated circuit device | |
| KR0124547Y1 (en) | Semiconductor device using multi-type leadframe | |
| JPS6245159A (en) | Semiconductor device | |
| JPH0590959U (en) | Semiconductor integrated circuit device | |
| JPH0752763B2 (en) | Resin-sealed semiconductor device |