JPS63209219A - Bidirectional interface circuit - Google Patents

Abstract

PURPOSE:To execute interface between different power source voltage bidirectionally by connecting first and second output buffer outputs to second and first level shifters respectively, and providing a mechanism to switch first and seconds I/O with each other by these output buffers. CONSTITUTION:The data inputted from an I/O terminal 102 are outputted from FETQ1 and Q2 to an I/O terminal 101 as first voltage amplitude type data. When the data input is executed from the I/O terminal 101 and the data are outputted to the I/O terminal 102, an I/O control signal is made into a high level. Thus, an output buffer 1 is turned off and an output buffer 5 is turned on. As the result, the flow of the data is reversily applied with voltage-amplitude conversion and inputted and outputted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interface circuit, and particularly to an interface circuit that bidirectionally transfers data between multiple integrated circuits driven by different power sources by using a voltage conversion circuit. Regarding.

[Conventional technology]

Conventionally, this type of interface circuit combines two I10 terminals as shown in FIG. The user selects whether to output the data or to output the data from 302 using 301 as an input terminal. still,
The logic levels of 301, 302, 303 and the integrated circuit are the same.

By stacking these in several stages, as shown in Fig. 4, 401.
Using the ability to select whether to transfer data from 404 to 403 or from 403 to 404 using the terminal 402, the ROM of the microcomputer
, used for interfacing RAM and data buses, and the like.

[Problem that the invention seeks to solve]

The conventional interface circuit described above makes the logic level of its own circuit the same as that of the integrated circuit, performs 1.10 switching using a control signal, and exchanges data between multiple integrated circuits. A drawback is that bidirectional data transfer between multiple integrated circuits with power supplies is not possible.

[Means for solving problems]

The interface circuit of the present invention includes a first output buffer that outputs to the first voltage amplitude system, a second output buffer that outputs to the second voltage amplitude system, and a second output buffer that outputs the first voltage amplitude to the second voltage amplitude system. a second level shifter for converting into
a first level shifter that converts the voltage amplitude of the first . The outputs of the second output buffers are connected to the second and first level shifters, respectively, and these output buffers connect the outputs of the first and second level shifters respectively. Since it has a mechanism for switching the second I10, it is possible to interface between different power supply voltages in both directions.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. 1
01 is an integrated circuit with a certain voltage amplitude system (logical amplitude),
The input/output terminal (hereinafter referred to as I10) for receiving and passing data is
terminal). 102 is an integrated circuit having a voltage amplitude system different from that of 101, and I1 which receives and transfers data.
0 terminal.

104 is a terminal that provides the same power supply potential as the integrated circuit connected to 101, and 105 is a terminal that provides the same power supply potential as the integrated circuit connected to 102. 106 is a ground. 103 is an I10 control terminal. This first embodiment is an example in which the low power supply voltage is made common to the ground level.

A first voltage amplitude system integrated circuit (for example, 3V system) is connected to the I10 terminal 101, and a second voltage amplitude system integrated circuit (for example, 5V system) is connected to the I10 terminal 102. When setting the ground level to I10 control terminal 103,
The I10 terminal 102 serves as an input and the I10 terminal 101 serves as an output terminal. The data, which is the second voltage amplitude input from the I10 terminal 101, is converted to the first voltage amplitude via the level shifter 2, passes through the output buffer 1, and is sent from the I10 terminal 101 to the first voltage amplitude system integration. Output to the circuit. I
10 control terminal 103 is set to the same level as the power supply voltage of the second voltage amplitude system]05, the I10 terminal 101 becomes the input terminal, and the data with the first voltage amplitude is transferred to the second voltage amplitude. Since the I10 terminal 102 is converted and set as an output terminal, it is output from the output buffer 5 to the second voltage amplitude system integrated circuit connected to the I10 terminal 102.

Next, the operation will be explained in detail. The control signal given to the 110 control terminal 103 is set to the ground level, the I10 terminal 102 is input, and the I10 terminal 10
1 is the output. This control signal is input to the NOR gate (Gto) via the NAND gate (E) and inverter (G9) of the output buffer-5;
, Gio output, P type FETQ, 5, N type FET
While turning off QI6, level shifter 3
P is input to inverter G6 and N-type FET Q1o.
Type FETQ7. The voltage amplitude is converted by Q9N-type FETs Qg and Qlo, and output to NAND through the output buffer's N6-OR gate G3 and inverter G2.
It is given to gate G1. On the other hand, the data input from the I10 terminal 102 is sent to the inverter G of the level silator 2.
5 and N-type FETQ6 and P-type FETQ3,
G5, G6 are input to P-type FETQ3, G5, N-type FETQ4. The voltage amplitude is converted by G6, and the gate is turned on by the control signal of output buffer-1 through NAND gate E and NOR gate E, and then output P-type FET Q1 and N-type FETQ2.
are applied to the FETs Ql and G2 and outputted to the I10 terminal 101 as data of the first voltage amplitude system.

Data is input from I10 terminal 101, and data is input from I10 terminal 102.
When outputting data to the output buffer 1, set the I10 control signal to high level to turn the output buffer 1 off.
F, and the output buffer 5 is turned on. As a result, the data flow is input/output after undergoing voltage amplitude conversion in the opposite manner as described above.

Next, a second embodiment is shown in FIG. This is an example in which a higher power supply potential 206 is set to the ground level compared to the first embodiment. The operation is exactly the same as that described using FIG. 1, except that the operating potential is a negative potential. In addition, 2
01 is the first I10 terminal, 202 is the second I10 terminal,
203 represents a control terminal, 21 and 25 represent output buffers, and 22 to 24 represent level shifters, respectively. 204 is a negative power supply terminal of the first voltage amplitude system;
205 indicates a negative power supply terminal of the second voltage amplitude system.

〔Effect of the invention〕

As explained above, the present invention connects a plurality of integrated circuits with different power supply potentials and the interface circuit of the present invention, and
By setting the output terminal with the 0 control terminal,
It has the effect of bidirectionally converting data from one logical level to another. Furthermore, the two I10 terminals can be connected to any different power supply voltage system by two level shifters and two output buffers that also perform I10 switching control. For example, considering the connection conditions of each 10 terminal for different power supply voltages, for example, a voltage amplitude system that is lower than the voltage amplitude system connected to the other I10 terminal must be connected to one I10 terminal. It has the effect of being good without it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram not showing a second embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional interface circuit. FIG. 4 is a block diagram in which conventional interface circuits are stacked to transfer data from a plurality of integrated circuits in both directions. 1.5, 11.15 are output buffers -12, 3° 4.1
2, 13, 14 are level shifters, 101° 201 is an I10 terminal connected to the first voltage amplitude system integrated circuit, 102, 20
2 is a second voltage amplitude system integrated circuit (71110 terminal, 1
03', 203 are control terminals, 104 is the + side power supply terminal of the first voltage amplitude system, 105 is the + side power supply terminal of the second voltage amplitude system, 106 is the ground level, and 204 is the first voltage amplitude system One side power supply terminal, 205, one side power supply terminal of the second voltage amplitude system, 206, ground level, 30
1.302 is the I connected to the integrated circuit at the same power supply potential.
Terminal 10, 303 is a control terminal.

Claims (1)

[Claims] In a circuit that interfaces between a plurality of integrated circuits, an output is connected to a first input/output terminal that is input to or output from a first voltage amplitude system integrated circuit, and the level-converted data is transmitted according to the level-converted control signal. The output is connected to a first output buffer that outputs and a second input/output terminal that inputs or outputs to a second voltage amplitude system integrated circuit, and outputs level-converted data according to a control signal input from the outside. a second output buffer; a first level shifter connected to the second input/output terminal and converting the level of data input from the second voltage amplitude system integrated circuit and inputting the data to the first output buffer; , a second level shifter connected to the first input/output terminal and level-converting the data input from the first voltage amplitude system integrated circuit and inputting the data to the second output buffer; a third level shifter that level-converts the control signal of the first output buffer and uses it as a control signal of the first output buffer; A bidirectional interface circuit characterized by providing a logical interface between system integrated circuits.