JPS63208948A - Task scheduling system for multi-processor system - Google Patents

Abstract

PURPOSE:To ensure a high-speed operation with the titled task scheduling system by securing such a constitution where a processor kept under a waiting state monitors a task ready queue via firmware and performing an automatic task scheduling job when a task kept under a ready exists. CONSTITUTION:A task A is kept under a run state with a processor 50 together with a task B is kept under a waiting state and a processor 60 is kept under a waiting state respectively. Under such conditions, when the task A gives a start request to the task B, the task B is connected to a task ready queue TRQ 71 of a main memory 70. A firmware mechanism 61 of the processor 60 refers to an instruction flag 73 set in the memory 70 when the processor 60 is kept under a waiting state and then checks the TRQ 71 to inspect the presence of a task kept under a ready state as long as an instruction is given for monitor of the TRQ. In such a case, the task B is detected and therefore a task dispatcher 62 performs a task scheduling job to extract the task B and to execute it via the processor 60.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a task scheduling method in a multiprocessor system.

(Prior Art) FIG. 3 shows a conventional multiprocessor system with two processors 10.20. It is now assumed that task A is in the RUN state S1, ie, being executed, in the processor 10, and task B is in the WAIT state S2. The processor 20 also has a CPU weight (WA).
IT). In this state, when task A, which is currently being executed on the processor 10, issues a start request to task B, and the wait state 182 of task B is released, task B is placed in the task ready state stored in the main memory 30. Ready (READ) connected to queue (TRQ) 31
Y) The state becomes $3. - Also, the processor 10 is a CPU
A processor in a wait state is checked, and if the processor 20 is in a CPU wait state as in this example, a 5IGP (signal processor) command is issued to the processor 20. This instruction is used to convey various information to other processors.

Now, the firmware mechanism 21 of the processor 20 in the CPU wait state handles interrupts (input/output interrupts, timer interrupts, 5IG interrupts,
It constantly monitors whether or not there is an interrupt (P interrupt) (step 41), and when an interrupt occurs, control is passed to the cutting handler (step 42). For example, 5I
If a 5IGP interrupt is accepted due to a GP command, 5
Control is passed to the IGP interrupt handler 22. As a result, a dispatching interrupt is generated from the 5IGP interrupt handler 22 to the task dispatch t23, and control is transferred to the task dispatcher 23. The task dispatch 1723 performs task scheduling in response to this interrupt. As a result, the task in the ready state, ie, task B, is taken out from the task ready queue 31, and the task B enters the run state S4 in the processor 20.

As mentioned above, in the conventional system shown in FIG.
Procedures were required such as the instruction to wake up the CPLI wait state processor and execute the 5IGP interrupt handler. For this reason, in conventional systems, high-speed task scheduling is difficult.

(Problems to be Solved by the Invention) As mentioned above, in the past, there was a problem that high-speed task scheduling was difficult because a complicated procedure was required from when a task became ready to when it was scheduled. Ta.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a task scheduling method in a multiprocessor system that can speed up task scheduling.

[Structure of the invention] (Means and effects for solving the problem) In this invention,
The main memory shared by multiple processors includes a task ready queue for managing tasks in a ready state, an address storage section for storing real addresses of entries in the task ready queue, and whether or not to monitor the task ready queue. A firmware mechanism for monitoring the task ready queue is provided in each processor, and when the own processor is in a CPtJ wait state and the instruction flag is in a task ready queue monitoring instruction state, The real address stored in the address storage unit is used to monitor the task ready queue, and when the presence of a ready task is detected, a dispatching interrupt is generated to the task dispatcher, thereby performing task scheduling. .

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the present invention is applied. In the figure, 50.60 is a processor, 70 is a processor 50.
(This is the main memory shared by 30.

The above [70] includes a task ready queue (TRQ) 71 for managing tasks in a ready state, an address storage section 72 for storing the real address of an entry (entrance, start position) of the task ready queue 71, and a task ready queue (TRQ) 71 for managing tasks in a ready state. An instruction flag 73 for instructing whether or not to monitor the ready queue 71
is depicted. On the other hand, the processor 60 has a waiting status! l! A firmware mechanism 61 that monitors the task ready queue 71 as necessary when the CPU is in a CPU wait state, and a task dispatcher 62 that performs task scheduling are provided. The processor 50 also includes a processor 6.
Firmware mechanism in 061. A task dispatcher (not shown), which is a firmware mechanism similar to the task dispatcher 62, is provided. In addition, in Figure 1,
811 indicates that task A is in the RUN state.
812 indicates that task B is in a WAIT state, 813 indicates that task B is in a READY state, and S14 indicates that task B is in a RUN state.

Next, the operation of one embodiment of the present invention will be explained with reference to the flowchart shown in FIG. Now task A is processor 5
At 0, it is in run form B811 (i.e. it is running)
, task B is in the waiting state S12. It is also assumed that the processor 60 is in a CPU wait state.

In this state, task A being executed by the processor 50
When a startup request is issued to task B from , and the status fulls12 of task B is released, task B is placed in the task ready queue (TRQ) 71 stored in the main memory 70.
(Specifically, Task B's Task IIJ Il
The main memory storage address of l block is task ready queue 7
1) and enters the ready state 813.

On the other hand, when the processor 60 is in the CPU wait state as described above, the firmware m structure 61 of the processor 60 interrupts (input/output interrupt, timer interrupt, 5IGP interrupt) as shown in the flowchart of FIG.
If there is an interrupt, the interrupt is passed to the interrupt handler corresponding to the interrupt type (step 82).If there is no interrupt, the processor The firmware mechanism 61 of 60 refers to the instruction flag 73 stored in the main memory 70 (step 83) and checks whether there is a task ready queue (TRQ) monitoring instruction (step 584).

If TRQ monitoring is instructed by the instruction flag 73, the firmware mechanism 61 refers to the entry (entrance) in the task ready queue (TRQ) 71 specified by the real address stored in the address storage unit 72 (step 85); Whether there is a task in the ready state (l
(step 86). if,
If there is no task in the ready state, the process returns to step 81. This is determined by the instruction flag 13.
The same applies when R0II is not specified. On the other hand, when task B becomes connected to the task ready queue 71 as described above, the firmware mechanism 61 performs step 86. The existence of a ready state task (task B) is determined in step 87, and a dispatching interrupt is generated to the task dispatcher 62 (step 87). Due to this interrupt, the task dispatcher 23 performs task scheduling, and as a result, the task ready queue 31
A task in a ready state, ie, task B, is taken out from the processor 20, enters a run state 814, and begins execution. It goes without saying that when the processor 50 is in the CPU wait state, the process shown in the flowchart of FIG. 2 is executed in the processor 60.

Although a multiprocessor system configured with two processors has been described above, the present invention is of course applicable to a multiprocessor system configured with three or more processors. Furthermore, the present invention is applicable not only to task scheduling but also to scheduling routines within the O8 (operating system) related to execution priority.

[Effects of the Invention] As detailed above, according to the present invention, the processor in the CPU wait state monitors the task ready queue by itself using its firmware mechanism, and when there is a task in the ready state, the processor automatically monitors the task ready queue. Since task scheduling is performed in advance, the run state processor detects the CPtJ wait state processor and
Activate the CPLJ wait state processor with the instruction;
Compared to the conventional method in which task scheduling is performed by executing a 5IGP interrupt handler, task scheduling can be performed more quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the present invention is applied, FIG. 2 is a flowchart for explaining the operation of a processor in a CPtJ wait state in the system of FIG. 1, and FIG. 4 is a block diagram showing a conventional multiprocessor system, and FIG. 4 is a flowchart for explaining the operation of a processor in a CPU wait state in the system of FIG. 50, 60... Processor, 61... Firmware mechanism, 62... Task dispatcher, 10...
Main storage, 11... Task ready queue, 12... Address storage section, 13... Instruction flag. Applicant's representative Patent attorney Takehiko Suzue 50, Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In a multiprocessor system including a plurality of processors, a task ready queue is placed in a main memory shared by the plurality of processors for managing tasks in a ready state, and an entry in the task ready queue is placed in the main memory. an address storage unit that stores the real address of the task ready queue; an instruction flag placed in the main memory that instructs whether or not to monitor the task ready queue; and a firmware mechanism placed in each of the processors; When the CPU is in a wait state and the instruction flag is in a task ready queue monitoring instruction state, the task ready queue is monitored using the real address stored in the address storage section, and the existence of a task in a ready state is detected. Then, it is equipped with a firmware mechanism that generates a dispatching interrupt to the task dispatcher,
A task scheduling method for a multiprocessor system, characterized in that task scheduling is performed in response to dispatching interrupts from the firmware mechanism.