JPS6320777A - Test system for data recording/reproducing device - Google Patents

Abstract

PURPOSE:To perform not only a test for both recording and reproducing system processing circuits but also a test for a reproducing system only and to improve the test reliability for a data recording/reproducing device, by connecting a RAM or a ROM where test data including known errors is recorded in place of a recording/reproducing mechanism. CONSTITUTION:The RAM Ma is connected to a demodulation, circuit 5 via a switch circuit W and the test data is written M the RAM Ma via a recording system processing circuit R. Then the test data is read out and looped back to a host processor H via a reproducing system processing circuit P for test of both circuits R and P. Then the ROM Mo where the test data including known errors is previously written is connected to the circuit 5. The error correcting and detecting actions of a circuit 6 are confirmed and the reliability is improved with a test for a data recording/reproducing device.

Description

[Detailed Description of the Invention] (Summary) A storage device connected in place of the recording/playback mechanism of a data recording/playback device is provided, and by using this storage device as a random access memory, a recording system processing circuit can be connected. The reproduction system processing circuit was tested by making the storage device a read-only memory.

(Industrial Application Field) The present invention relates to a test method for a data recording/reproducing device that records and reproduces digital data on a high-density recording medium such as an optical disk or a magneto-optical memory.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a data recording/reproducing apparatus to which the present invention is applied. Data to be recorded sent from the host processor H via the bidirectional lotus B is
A recording system processing circuit R including an error correction/detection code circuit 2 that interleaves data from the controller 1 and adds an error correction code and an error detection code, and a modulation circuit 3 that modulates a signal suitable for recording and adds a synchronization signal. The data is then recorded on a recording medium such as an optical disk or a magneto-optical memory in a recording/reproducing mechanism S.

When reproducing data recorded on a recording medium by the recording/reproducing mechanism S of this data recording/reproducing device, the demodulation circuit 5 that detects the synchronization of the signal read from the recording medium and demodulates the signal is mistaken. A reproduction system processing circuit P including a decoding circuit 6 that performs correction/detection and deinterleaving reproduces the data recorded on the recording medium, and transmits the reproduced signal from the controller 1 to the host via the bidirectional bus B. Transfer to processor H.

In order to test the recording system processing circuit and the reproduction system processing circuit of such a data recording/reproduction device, conventionally the recording and reproduction mechanism S is bypassed and the output side of the modulation circuit 3 and the input side of the demodulation circuit 5 are connected. A switching circuit W is provided to directly connect the data to the data recording/reproducing device, and the data is processed by the recording system processing circuit R and the reproduction system processing circuit P, and then looped to the host processor H. The operation of the data recording/reproducing apparatus was tested by backing up the loop-hacked data and the known data using a host processor.

In the recording/reproducing apparatus shown in FIG. 3, when a synchronization error occurs in the demodulation circuit 5, the error flag notifies the controller l of the occurrence of a synchronization error, and the decoding circuit 6
Then, when a data error is detected by error correction or error detection, a flag is used to notify the controller 1 of the occurrence of the error.

Further, the data recording/reproducing device is controlled by a control processor C provided therein. 1).

[Problems to be Solved by the Invention] In the recording/reproducing device as described above, a bidirectional lotus B is generally used for data transfer between the host processor H and the data recording/reproducing device A. Therefore, it is not possible to transfer both data input to and output from the recording/reproducing apparatus A at the same time. Further, even when a pair of unidirectional buses are used, bidirectional transfer may not be possible at the same time because input and output cannot be performed simultaneously in the memory on the host processor side.

Since normal recording and playback are performed via a recording medium, the signal transmitted from the host processor H to the controller 1 and the signal transmitted from the controller 1 to the host processor H do not exist at the same time. and the controller as shown above.
There is no practical problem even if you connect with .

However, in the above-mentioned test method in which the test is performed without going through the recording and reproducing mechanism S that writes and reads from the recording medium, even if the processing time in the recording system processing circuit and the reproduction system processing circuit described above is taken into account, Test data sent from the host processor to controller 1 and loopback data sent from the controller to the host processor after processing this test data may exist on bidirectional bus B at the same time.

Therefore, in order to obtain a time difference that does not exist simultaneously on the 8 big noise data and the loopback data on the bidirectional lotus B, when executing the test, the operating speed of each circuit under test is lowered, etc. It is necessary to operate at different timings, and therefore there is a drawback that operation under normal conditions cannot be confirmed.

In addition, in such conventional test methods, the recording system processing circuit and the reproduction system processing circuit are tested together, so even if an error occurs in the recording system processing circuit, this error cannot be corrected in the reproduction system processing circuit. In such cases, there are drawbacks such as the host processor being unable to recognize an abnormality in the recording processing circuit, or being unable to test only the reproduction processing circuit.

[Means for solving problems]

As shown in the principle diagram of FIG.
o was provided, and this storage device sent out data instead of this recording/reproducing mechanism S during testing.

By using a random access memory Ma as this storage device, known test data is supplied from the host processor to this data recording/reproducing device, and the recording system processing circuit R and the reproduction system processing circuit P
The test can be conducted in conjunction with the above.

Furthermore, by using a read-only memory MO that stores data containing various known errors as the storage device, it is possible to test the reproduction system processing circuit P that processes data read from the recording and reproduction mechanism.

[For production]

As shown in the principle diagram of FIG. 1, known test data is input from the host processor H to the data recording/reproducing device A, and the data processed by the recording system processing circuit R is stored in the random access memory Ma. Then, the functions of the recording system processing circuit R and the reproduction system processing circuit P of this data recording/reproducing apparatus A are activated by processing the data transferred from this random access memory in the reproduction system processing circuit and returning it to the host processor H. Can be tested.

In this way, the test data supplied from the host processor to the data recording/playback device under test and the processed test data sent back from the data recording/playback device to the host processor can exist on the lotus at different times. In addition, the host processor can send out existing test data and receive processed test data at different times, which prevents interference of these data or conflicting accesses of the host processor's memory. do not have.

However, if you store data that contains known errors or use a single-only memory MO instead of the recording/reproducing mechanism S,
The processing function of the reproduction processing circuit P can be tested by processing the data read from the read-only memory by the reproduction processing circuit P and sending it back to the host processor.

In addition, by storing data with synchronization abnormalities in this lead-on "J memory Mo, it is possible to test the synchronization processing ability of the playback system processing circuit, but as this data, frame synchronization signals are generated in bursts. By writing missing data, you can check the synchronization signal interpolation that is performed when synchronization is lost due to a burst error, and by writing data with the position of the frame synchronization signal shifted, the synchronization signal can be checked. It is possible to check the detection width of the prediction function that occurs when detecting , and by writing data that includes a frame synchronization signal with bit errors, it can be confirmed that synchronization detection is performed for bit errors allowed by the above prediction function. can.

〔Example〕

FIG. 2 is a description for applying the test method according to the present invention!
FIG. 2 is a block diagram showing an embodiment of a data recording/reproducing device including a random access memory Ma and a read-only memory Mo, and shows the operation of elements other than the random access memory Ma, the read-only memory Mo, and the switching circuit W. are as described above with respect to FIG. 3, and corresponding elements are given the same reference numerals.

The random access memory ~1a stores the data output from the modulation circuit 3 and outputs the test data to the demodulation circuit 5, and the read-only memory Mo has test data containing known errors written, and the switching circuit W selectively connects the output side of the modulation circuit 3 and the input side of the demodulation circuit 5 to either the recording/reproducing mechanism S, the random access memory Ma, or the single-only memory MO.

Now, random access memo + 7 M by switching circuit W
A test in a state where a is connected to the input terminal of the demodulation circuit 5 will be explained. Note that ■ and ■ in the figure are symbols indicating the flow of data corresponding to steps 1 and 2 described below.

First, in step 1, known test data is transferred from the host processor H to the code circuit 2 via the controller 1,
The code circuit 2 interleaves the test data along with adding an error detection code and error correction code, and the modulation circuit 3 inserts a synchronization signal into the test data to which each code is added, and at the same time modulates it into a recording signal. and writes it into the random access memory Ma.

When the above step 1 is completed, the controller 1 and the bidirectional lotus B are in a state where data input/output is not performed, and then in step 2, the following operations are performed.

The test data written in the random access memory Ma is read out, and the demodulation circuit 5 detects a synchronization signal from the test data modulated into this recorded signal, synchronizes, demodulates the test data, and a synchronization error occurs. If so, an error flag is output to the controller l to notify it, and the demodulated test data is output to the decoding circuit 6.

In the decoding circuit 6, error correction and error detection are performed on the demodulated and input test data, and at this time, if 8-bit correction is performed, an error correction flag is set, and if an error is detected, an error detection flag is set. The flag is output to the controller 1 and the test data is output to the controller l.

In this way, the test data that has passed through each circuit is looped back from the controller 1 to the host processor H via the same bus B, and the recording/reproducing device operates according to each error flag and detection flag. Check.

As described above, by looping back through the operations of step 1 and step 2 via the random access memory, the test data passing through each circuit is output from the host processor and stored in the random access memory at N+B. After that, the random access memory outputs the data from the random access memory via each circuit and the controller, so loopback can be performed at the same timing as normal circuit operation.

Next, a test with the read-only memory 'v10 connected by the switching circuit W will be described.

In the read-only memory Mo, when test data whose number of error corrections and error detections are known in advance is modulated by the modulation circuit 3, it is written in the form of a signal pattern.

When such test data is read from the read-only memory MO and input to the demodulation circuit 5, the same operation as step 2 of the first embodiment is performed, and the error-corrected test data is input to the host processor H. be done.

On the other hand, since the test data read from the read-only memory MO contains known errors, the decoding circuit 6 performs error correction or error detection as the circuit operates, and each flag is sent each time. The controller 1 counts each flag and transfers the result to the host processor H, which compares it with the pre-known number of error corrections or error detections. It is possible to check the error correction and error detection operations of the decoding circuit.

Also, if known test data in which the frame synchronization signal is missing in a burst form is written in the read-only memory Mo, and this test data is read out and input to the demodulation circuit 5 for processing, this demodulation circuit If the synchronization detection operation is performed normally, interpolation is performed where the synchronization signal of the test data is missing and a synchronization error flag is output, so this synchronization error flag must be counted by controller 1 or host processor H. The operation of interpolation of the synchronization signal performed in response to loss of synchronization due to the occurrence of a burst error can be confirmed.

Similarly, by writing known data in which the position of the frame synchronization signal is shifted as test data, if the synchronization signal with the shifted position falls outside the detection range of the prediction function when detecting the synchronization signal, the synchronization Since an error flag is output, it is possible to check whether synchronization detection is performed within the detection width of the prediction function using this synchronization error flag, and also,
By writing data that includes a frame synchronization signal with bit errors, synchronization detection is performed for synchronization signals with bit errors within the range allowed by the prediction function, and synchronization detection with bit errors outside the range allowed by the prediction function is performed. Since synchronization detection is not performed on the signal and a synchronization error flag is output, it is possible to confirm whether or not synchronization detection will be performed for bit errors allowed by the prediction function using this synchronization error flag.

〔Effect of the invention〕

According to the present invention, when loop hacking test data, all of this test data is once stored in a storage device, and then output to the host processor, and circuit operation is performed at the same timing as when loop hacking is performed to create a loop bank of test data. In addition, test data containing known errors can be passed through the reproduction system processing circuit and then heli-fied to the host processor, thereby providing more information about the synchronization detection operation of the demodulation circuit or the error correction operation of the decoding circuit. It is possible to perform highly accurate tests.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing the configuration of a data recording/reproducing device in an embodiment, and Fig. 3 is a block diagram showing the configuration of a data recording/reproducing zH to which the present invention is applied. It is. G is a host processor, A is a recording/reproduction device, C is a control processor, R is a recording system processing circuit, P is a reproduction system processing circuit, S is a recording/reproduction mechanism, Ma is a random access memory, and Mo is a read-only memory. be.

Claims (4)

[Claims] (1) A recording system processing circuit (R) including a code circuit that adds a code for error correction and detection to data to be recorded and performs interleaving, and a modulation circuit that modulates the data to which this code is added; A playback system that includes a recording/reproducing mechanism (S) that records and reads out the modulated data, a demodulating circuit that demodulates the data read from the recording/reproducing mechanism, and a decoding circuit that performs error correction/detection and deinterleaving. In order to test the data recording/reproducing device (A), which includes a system processing circuit (P) and a control processor (C) for controlling these, known test data is transferred from the host processor (H) to this recording/reproducing device. The data is supplied to the playback device, processed by the recording system processing circuit, and then stored in a random access memory (Ma), and the data read from the random access memory is supplied to the playback system processing circuit and processed. The recording system processing circuit and the reproduction system processing circuit of the data recording/reproducing apparatus are tested by sending the results back to the host processor and comparing them with the test data sent out by the host processor. Test method for data recording/playback equipment. (2) A recording and reproducing mechanism (S) that reads data recorded on a recording medium, a demodulation circuit that demodulates the data read from this recording and reproducing mechanism, and a decoding circuit that performs error correction/detection and deinterleaving. In order to test a data recording and reproducing device (A) that includes a reproducing system processing circuit (P) and a control processor (C) for controlling these, a lead that transmits data in place of the recording and reproducing mechanism described above is used. A read-only memory (M_o) is provided, and the output of this read-only memory is supplied to the reproduction system processing circuit for processing, and the result is sent to the host processor to test the reproduction system processing circuit. A test method for data recording/reproducing devices characterized by the following. (3) Claim 2, characterized in that the read-only memory stores data containing known errors.
Test method for data recording/playback equipment described in Section 1. (4) A patent claim characterized in that the read-only memory stores data in which the frame synchronization signal is misaligned, data in which the frame synchronization signal has a bit error, or data in which the frame synchronization signal is deleted. A test method for the data recording/reproducing device described in item 2.