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JPS63207181A - semiconductor materials - Google Patents

semiconductor materials

Info

Publication number
JPS63207181A
JPS63207181A JP62041201A JP4120187A JPS63207181A JP S63207181 A JPS63207181 A JP S63207181A JP 62041201 A JP62041201 A JP 62041201A JP 4120187 A JP4120187 A JP 4120187A JP S63207181 A JPS63207181 A JP S63207181A
Authority
JP
Japan
Prior art keywords
layer
less
film
poly
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62041201A
Other languages
Japanese (ja)
Inventor
Masaki Hiroi
正樹 廣居
Masumitsu Ino
益充 猪野
Shuya Abe
修也 阿部
Noriyuki Terao
典之 寺尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Original Assignee
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Research Institute of General Electronics Co Ltd, Ricoh Co Ltd filed Critical Ricoh Research Institute of General Electronics Co Ltd
Priority to JP62041201A priority Critical patent/JPS63207181A/en
Publication of JPS63207181A publication Critical patent/JPS63207181A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]

Abstract

PURPOSE:To enable the high-speed operation of a transistor when a TFT is manufactured, and to obtain the excellent reproducibility of electric physical properties by forming a polysilicon layer in a thin layer of 1000Angstrom or less and bringing the smoothness of the polysilicon layer to + or -20Angstrom or less. CONSTITUTION:In a semiconductor material in which a poly-Si layer 2 used as an active layer for a TFT (a thin-film transistor) is shaped onto a transparent insulating substrate l, the poly-Si layer 2 is formed in a thin-film of 1000Angstrom or less, and the smoothness of the layer 2 is brought to + or -20Angstrom or less. That is, grain size can be scaled up by a change into the thin-film, thus increasing mobility. Leakage currents from a gate electrode at the time of the formation of the TFT can be reduced extremely by the smoothing of the surface while the film having excellent reproducibility can be shaped.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は透明絶縁基板上に薄膜トランジスタの活性層と
して使用するポリシリコン(以下、poly−3i)層
が形成された半導体材料に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor material in which a polysilicon (hereinafter referred to as poly-3i) layer used as an active layer of a thin film transistor is formed on a transparent insulating substrate.

〔従来技術〕[Prior art]

一般に、等倍イメージセンサ−や液晶ディスプレイ等を
駆動する大面積透明絶縁基板上に高密度に配置された薄
膜トランジスタ(以下、TPTと称する)あるいはS’
OIは、その高速応答性能が最も重要である。通常、T
PTの活性層やS○工のSi膜を構成する半導体膜とし
てはアモルファスSi (以下、a−5i:H)膜やp
oly −5i膜が用いられているが、高速スイッチン
グ速度が要求される場合にはa −si: H膜をより
もキャリア移動度の大きいpoly −Si膜が用いら
れている。そして、このようなpoly −Si膜のキ
ャリア移動度をより大きくするために、poly −S
i膜を薄膜化して熱処理し、結晶粒径をより大きくする
ことが試みられている。しかし、poly −Si膜は
通常、減圧CVD法等により透明絶縁基板上に形成され
るため、その表面性があまり良くない。従って、このp
oly −Si膜を活性層としてその上にゲートを形成
した場合、ゲートリーク等の不具合が生じやすいという
問題点を有するものであった。
In general, thin film transistors (hereinafter referred to as TPTs) or S'
The most important aspect of OI is its high-speed response performance. Usually, T
Semiconductor films constituting the active layer of PT and the Si film of S○ process include amorphous Si (hereinafter referred to as a-5i:H) film and p
Although an oly-5i film is used, when a high switching speed is required, a poly-Si film, which has higher carrier mobility than an a-si:H film, is used. In order to further increase the carrier mobility of such a poly-Si film, poly-S
Attempts have been made to make the i-film thinner and subject it to heat treatment to increase the crystal grain size. However, since the poly-Si film is usually formed on a transparent insulating substrate by low pressure CVD or the like, its surface properties are not very good. Therefore, this p
When an oly-Si film is used as an active layer and a gate is formed thereon, problems such as gate leakage tend to occur.

〔目   的〕〔the purpose〕

本発明は上記に示した従来の問題点を改善し、等倍イメ
ージセンサ−や結晶ディスプレイ等を駆動するTPTを
作製した場合にトランジスタの高速動作が可能で、電気
特性の再現性が良く、製造歩留り並びに品質が向上する
半導体材料を提供することを目的とするものである。
The present invention improves the above-mentioned conventional problems and enables high-speed operation of transistors, good reproducibility of electrical characteristics, and easy manufacturing when manufacturing TPTs for driving 1-magnification image sensors, crystal displays, etc. The purpose is to provide semiconductor materials with improved yield and quality.

〔構  成〕〔composition〕

本発明は透明絶縁基板上にTPTの活性層として使用す
るpoly −Si層が形成された半導体材料において
、前記poly −Si層が1000Å以下の薄層をな
し、かつその平滑度が±20Å以下であることを特徴と
するものである。
The present invention provides a semiconductor material in which a poly-Si layer used as an active layer of TPT is formed on a transparent insulating substrate, wherein the poly-Si layer is a thin layer of 1000 Å or less and has a smoothness of ±20 Å or less. It is characterized by certain things.

本発明者らは上記課題を達成すべく種々検討を重ねた結
果、透明絶縁基板上のpoly −Si層の膜厚を10
00Å以下となし、かつその平滑度を±20Å以下とす
ることにより、次のような利点が得られることを知見し
た。すなわち、■薄膜化することによりグレインサイズ
を大きくできる。
The present inventors have conducted various studies to achieve the above object, and as a result, the film thickness of the poly-Si layer on the transparent insulating substrate was increased to 10%.
It has been found that the following advantages can be obtained by setting the thickness to 00 Å or less and the smoothness to ±20 Å or less. That is, (1) the grain size can be increased by making the film thinner.

■従って移動度が大きくなる。■表面の平滑化によりT
PTを形成した場合のゲート電極からのリーク電流を極
力少なくできる。■平滑化により再現性の良い膜ができ
る。本発明はこれら知見に基づいて完成したものである
■Therefore, mobility increases. ■ T by smoothing the surface
When PT is formed, leakage current from the gate electrode can be minimized. ■ Smoothing creates a film with good reproducibility. The present invention was completed based on these findings.

このように本発明では、透明絶縁基板上のpoly −
Si層の膜厚とともに表面の平滑度を所定の値とするも
のであり、膜厚もしくは平滑度のみを所定値にしたとし
ても所期の目的は達成し得ないものである。なお、po
ly −Si層の膜厚は1000Å以下とするが、好ま
しくは500Å以下とする。また、平滑度は±20Å以
下とするが、好ましくは±10Å以下とする。
In this way, in the present invention, poly-
The thickness and smoothness of the surface of the Si layer are set to a predetermined value, and even if only the thickness or smoothness is set to a predetermined value, the intended purpose cannot be achieved. In addition, po
The thickness of the ly -Si layer is set to be 1000 Å or less, preferably 500 Å or less. Further, the smoothness is set to be ±20 Å or less, preferably ±10 Å or less.

以下に、このような所定の膜厚および平滑度をもった透
明絶縁基板上のpoly −Si層を得るいくつかの手
段を説明する。
Below, several means for obtaining a poly-Si layer on a transparent insulating substrate having such a predetermined thickness and smoothness will be explained.

第1図はその一例を示す工程説明図である。FIG. 1 is a process explanatory diagram showing an example thereof.

第1図において、透明絶縁基板1上にpoly −5i
層2を成膜する(第1図(a))。このpoly −S
i層2は、例えば次に示す如き条件による減圧CVD法
により、膜厚1600〜1700人程度に成膜する。
In FIG. 1, poly-5i is placed on a transparent insulating substrate 1.
Layer 2 is deposited (FIG. 1(a)). This poly-S
The i-layer 2 is formed to a thickness of approximately 1,600 to 1,700 layers by, for example, a low pressure CVD method under the following conditions.

温度  =560〜730℃ SiH4濃度=濃度−10〜100%ガス: N、 o
rH,)流量  =75〜700secm 圧力  :0,1〜0.5Torr 次に、poly−8i層2上に塗布型のSin、層3、
例えば東京応化層OCD −S 1−80000を表面
が平滑になるように塗布する(第1図(b))。
Temperature = 560~730°C SiH4 concentration = concentration -10~100% Gas: N, o
rH,) Flow rate = 75 to 700 sec Pressure: 0.1 to 0.5 Torr Next, on the poly-8i layer 2, coated Sin, layer 3,
For example, Tokyo Ohka Layer OCD-S 1-80000 is applied so that the surface is smooth (FIG. 1(b)).

(b)工程で得られたSiO2層3を下層のpoly 
−5i層2の凸部がSiO,層3の表面に一致する程度
にまでエツチングにより除去する(第1図(C))。
(b) The SiO2 layer 3 obtained in step
The -5i layer 2 is removed by etching to the extent that its convex portions coincide with the surface of the SiO layer 3 (FIG. 1(C)).

この時、poly −Si層凸部上端とSiO□層3の
残部によって表面が平滑になっている。
At this time, the surface is made smooth by the upper end of the convex portion of the poly-Si layer and the remainder of the SiO□ layer 3.

(c)工程で得られたものを、例えば下記の如き条件で
熱酸化する。
The material obtained in step (c) is thermally oxidized, for example, under the following conditions.

温度   :1025℃ 0□流量  :300secm、昇温時: 30scc
mN2流量  : I Q /win(降温時)この熱
酸化により、平滑表面より所定厚さのSiO□層3′が
形成され、これによってSiO□層3′層面1表面O□
N3′とpoly −Si層2との界面も平滑になる(
第1図(d))。
Temperature: 1025°C 0□Flow rate: 300sec, temperature rising: 30scc
mN2 flow rate: I Q /win (when temperature decreases) Due to this thermal oxidation, a SiO□ layer 3' of a predetermined thickness is formed from the smooth surface, and as a result, the SiO□ layer 3' layer surface 1 surface O□
The interface between N3' and poly-Si layer 2 also becomes smooth (
Figure 1(d)).

(d)工程で得られたものをエツチングして、表層の5
in2J’ii3 ’ を除去すると、表面が平滑なp
oly −Si層2が得られる(第1図(e))。得ら
れるpoly −Si層2の膜厚は1000人程度であ
り、その表面平滑度は±20人程度のものとなる。
(d) Etching the material obtained in step 5 of the surface layer.
Removal of in2J'ii3' creates p with a smooth surface.
An oly-Si layer 2 is obtained (FIG. 1(e)). The thickness of the obtained poly-Si layer 2 is about 1000 mm, and its surface smoothness is about ±20 mm.

第2図は他の例を示す工程説明図である。FIG. 2 is a process explanatory diagram showing another example.

第2図において、透明絶縁基板1上に比較的厚い例えば
4000〜5000人程度のpoly −Si層2を減
圧CVD法により成膜する(第2図(a))。poly
−5i層2の成膜条件は第1図(a)工程のそれと同様
でよい。
In FIG. 2, a relatively thick poly-Si layer 2 of, for example, about 4,000 to 5,000 layers is formed on a transparent insulating substrate 1 by low pressure CVD (FIG. 2(a)). poly
The conditions for forming the -5i layer 2 may be the same as those in the process of FIG. 1(a).

(a)工程で得られたpoly−5i層2をドライエツ
チングにより、少しづつ除去する(第2図(b))。
The poly-5i layer 2 obtained in step (a) is removed little by little by dry etching (FIG. 2(b)).

この工程を継続し、最終的にpoly −Si層2の表
面が所望の1例えば±20人程度の平滑度が得られ、し
かも膜厚が1000Å以下となった時点でエツチング終
了する。これにより第2図(c)に示されるような所望
の材料が得られることになる。
This process is continued until the surface of the poly-Si layer 2 has a desired smoothness of about 1, for example, ±20 degrees, and the etching is finished when the film thickness is less than 1000 Å. As a result, a desired material as shown in FIG. 2(c) can be obtained.

かくして得られる半導体材料は透明絶縁基板1上にpo
ly −Si層2が1000Å以下の厚さで、しかもそ
の表面平滑度が±20Å以下であるため。
The semiconductor material thus obtained is placed on the transparent insulating substrate 1.
This is because the ly-Si layer 2 has a thickness of 1000 Å or less and a surface smoothness of ±20 Å or less.

この材料を用いてTPTを常法に従って作製すると、p
oly −Si層が活性層となり、この活性層は大きな
結晶粒径を有するため、キャリア移動度が大きくなり、
しかも表面が平滑であるためゲート電極からのリーク電
流が極力少なくでき、電気特性の再現性のよいTPTが
得られることになる。
When TPT is produced using this material according to a conventional method, p
The oly-Si layer becomes an active layer, and since this active layer has a large crystal grain size, carrier mobility becomes large,
Moreover, since the surface is smooth, leakage current from the gate electrode can be minimized, and a TPT with good reproducibility of electrical characteristics can be obtained.

〔効  果〕〔effect〕

以上のような本発明によれば、TPTを作製した場合に
トランジスタの高速動作可能で、品質および製造歩留り
が向上し、電気物性の再現性の良い半導体材料が得られ
るという効果を有する。
According to the present invention as described above, when a TPT is manufactured, the transistor can operate at high speed, quality and manufacturing yield are improved, and a semiconductor material with good reproducibility of electrical properties can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る半導体材料を作製する場合の一例
を示す工程説明図である。 第2図は本発明に係る半導体材料を作製する場合の他の
例を示す工程説明図である。 1・・・透明絶縁基板  2・・・poly −Si層
3.3′・・・5i02層 平ヨ弓艷・
FIG. 1 is a process explanatory diagram showing an example of manufacturing a semiconductor material according to the present invention. FIG. 2 is a process explanatory diagram showing another example of manufacturing the semiconductor material according to the present invention. 1...Transparent insulating substrate 2...poly-Si layer 3.3'...5i02 layer

Claims (1)

【特許請求の範囲】[Claims] 1、透明絶縁基板上に薄膜トランジスタの活性層として
使用するポリシリコン層が形成された半導体材料におい
て、前記ポリシリコン層が1000Å以下の薄層をなし
、かつその平滑度が±20Å以下であることを特徴とす
る半導体材料。
1. In a semiconductor material in which a polysilicon layer used as an active layer of a thin film transistor is formed on a transparent insulating substrate, the polysilicon layer is a thin layer of 1000 Å or less and its smoothness is ±20 Å or less. Characteristic semiconductor materials.
JP62041201A 1987-02-24 1987-02-24 semiconductor materials Pending JPS63207181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62041201A JPS63207181A (en) 1987-02-24 1987-02-24 semiconductor materials

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62041201A JPS63207181A (en) 1987-02-24 1987-02-24 semiconductor materials

Publications (1)

Publication Number Publication Date
JPS63207181A true JPS63207181A (en) 1988-08-26

Family

ID=12601803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62041201A Pending JPS63207181A (en) 1987-02-24 1987-02-24 semiconductor materials

Country Status (1)

Country Link
JP (1) JPS63207181A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04326512A (en) * 1991-04-25 1992-11-16 Tokyo Electron Ltd Forming method of doped thin film
US5712496A (en) * 1992-01-17 1998-01-27 Seiko Instruments, Inc. MOS Poly-Si thin film transistor with a flattened channel interface and method of producing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04326512A (en) * 1991-04-25 1992-11-16 Tokyo Electron Ltd Forming method of doped thin film
US5712496A (en) * 1992-01-17 1998-01-27 Seiko Instruments, Inc. MOS Poly-Si thin film transistor with a flattened channel interface and method of producing same
US5849612A (en) * 1992-01-17 1998-12-15 Seiko Instruments Inc. MOS poly-si thin film transistor with a flattened channel interface and method of producing same

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