JPS63207151A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63207151A JPS63207151A JP4071287A JP4071287A JPS63207151A JP S63207151 A JPS63207151 A JP S63207151A JP 4071287 A JP4071287 A JP 4071287A JP 4071287 A JP4071287 A JP 4071287A JP S63207151 A JPS63207151 A JP S63207151A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- etching
- mask
- opening
- opening section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000005337 ground glass Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 241000981595 Zoysia japonica Species 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000005338 frosted glass Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
最近のICの高集積化に伴い、配線の微細化も進み、配
線層の段差被覆性による品質が問題となってきた。As ICs have become more highly integrated in recent years, interconnections have become increasingly finer, and the quality of interconnect layers due to step coverage has become a problem.
この対策として、半導体基板表面の絶縁膜を開孔して内
部の素子電極又は導電体コンタクトに上層配線層を形成
して接続する場合に、開孔部の上縁円周部にテーパを設
けて、上層配線層の段差被覆性を良くする必要がある。As a countermeasure for this, when forming an upper wiring layer to connect an internal element electrode or conductor contact by opening a hole in the insulating film on the surface of a semiconductor substrate, a taper is provided at the circumference of the upper edge of the opening. , it is necessary to improve the step coverage of the upper wiring layer.
従来はこのテーパを設けるのに、ホトリソグラフィ技術
によりシリコン酸化膜上にマスクを形成した後に、NF
3+82の反応性ガスにレーザ光を当て生じた反応活性
種がシリコン酸化膜の開口部表面に吸着することによっ
て異方性エツチング反応が進み形成された円筒形の開口
部の上面に、更に等方性のウェットエツチング等を行っ
ていた。Conventionally, to provide this taper, a mask was formed on the silicon oxide film using photolithography technology, and then NF
The reactive active species produced by applying laser light to the 3+82 reactive gas adsorbs to the surface of the opening in the silicon oxide film, resulting in an anisotropic etching reaction. Sexual wet etching was performed.
上述した従来の半導体装置の製造方法は、絶縁膜の開孔
部の上縁にテーパを形成するウェットエツチング工程で
、絶縁膜の表面の汚染やダメージ等が原因となり、レー
ザ光によるエツチングの特長である洗浄かつダメージの
少ない絶縁膜を形成することは困難であるという問題が
あった。The conventional semiconductor device manufacturing method described above uses a wet etching process to form a taper at the upper edge of the opening in the insulating film, which may cause contamination or damage to the surface of the insulating film, which is a disadvantage of etching using laser light. There has been a problem in that it is difficult to form an insulating film that can be cleaned and has little damage.
本発明の目的は、全表面が洗浄な状態で、絶縁膜中にテ
ーパ部を有する開孔部が形成できる半導体装置の製造方
法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which an opening having a tapered portion can be formed in an insulating film while the entire surface is cleaned.
本発明の半導体装置の製造方法は、半導体基板上に開孔
部を有する絶縁膜を介して半導体素子の電極または配線
となる導体層を形成する工程を有する半導体装置の製法
方法において、前記絶縁膜の上に該絶縁膜よりエツチン
グ速度の遅い材料の層を堆積し、開孔部を設けてマスク
とする工程と、光の入射面が平坦で射出面が微細凸凹を
有する面である光拡散物体の板を前記マスクの上方に置
き上方からレーザ光を照射して前記絶縁膜をその厚さの
半分程度まで等方性エツチングを行う行程と、前記光拡
散物体を除いて前記開孔部の残りの絶縁膜を異方性エツ
チングして前記絶縁膜の下である前記導体層の露出させ
る工程と、前記マスクを除去し、前記等方性エツチング
された絶縁膜部分の厚さが半分程度になるまで前記絶縁
を表面からエツチング除去する工程と、前記導体層に接
続し前記絶縁膜上に延在する上層配線を形成する工程と
を含んで構成される。A method for manufacturing a semiconductor device according to the present invention includes a step of forming a conductor layer to serve as an electrode or wiring of a semiconductor element through an insulating film having an opening on a semiconductor substrate. A step of depositing a layer of material whose etching rate is slower than the insulating film on top of the insulating film and forming an opening to serve as a mask; and a light diffusing object whose light incident surface is flat and whose light exit surface has fine irregularities. A process of isotropically etching the insulating film to about half its thickness by placing the plate above the mask and irradiating laser light from above, and removing the light diffusing object and etching the remaining part of the opening. a step of anisotropically etching the insulating film to expose the conductor layer under the insulating film, and removing the mask so that the thickness of the isotropically etched insulating film portion is reduced to about half. and a step of forming an upper layer wiring connected to the conductor layer and extending over the insulating film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
第1図(a)に示すように、半導体基板1の表面にシリ
コン酸化膜2と多結晶シリコン層4と更に厚さ1μm程
度のシリコン酸化膜3を重畳し、最上層にホトレジスト
層5を形成する。As shown in FIG. 1(a), a silicon oxide film 2, a polycrystalline silicon layer 4, and a silicon oxide film 3 with a thickness of about 1 μm are superimposed on the surface of a semiconductor substrate 1, and a photoresist layer 5 is formed on the top layer. do.
ホトレジスト層5にはホトリソグラフィ技術によって通
訳的に開孔部6を形成する。Openings 6 are formed in the photoresist layer 5 by photolithography.
次に、第1図(b)に示すように、NF3−1−H2の
ように反応性ガス中でレーザ光8aを入射面が平坦なす
りガラス板7を通して発生する拡散透過光8bを開孔部
に照射する。Next, as shown in FIG. 1(b), the laser beam 8a is generated in a reactive gas such as NF3-1-H2 through the ground glass plate 7 with a flat incident surface, and the diffused transmitted light 8b is generated through the opening. irradiate.
ここで開孔部6から離れなすりガラス7からの拡散透過
光8bの一部が、ホトレジスト層5の開孔部6の下縁の
角と結ぶ左右の光線の下方向にまで照射されるので、レ
ーザ孔8aの拡散透過孔8bはシリコン酸化膜3の開孔
部直下のみならず横方向も照射される。Here, a part of the diffused transmitted light 8b from the frosted glass 7 away from the aperture 6 is irradiated downward to the left and right light beams connecting with the lower edge corners of the aperture 6 of the photoresist layer 5. The diffused transmission hole 8b of the laser hole 8a is irradiated not only directly below the opening of the silicon oxide film 3 but also in the lateral direction.
このHF3+H2ガス中のレーザ光8aの照射をシリコ
ン酸化層3のエツチングの深さが厚さの半分程度になり
、ホトレジスト層5の開孔部6の縁がひさし状になるよ
うに等方性エツチングを継続し、シリコン酸化膜3に中
底部3bとテーパ9を有する開孔部を形成する。Irradiation with the laser beam 8a in this HF3+H2 gas is performed isotropically so that the depth of etching of the silicon oxide layer 3 is about half of the thickness and the edge of the opening 6 of the photoresist layer 5 is shaped like an eaves. Then, an opening having a middle bottom portion 3b and a taper 9 is formed in the silicon oxide film 3.
次に、第1図(c)に示すように、すりガラス板7を除
き、ホトレジスト層5をマスクとし、HF3+H2ガス
中でレーザ光8aを照射して異方性エツチングすること
により、多結晶シリコン層4の露出部10を形成する。Next, as shown in FIG. 1(c), the ground glass plate 7 is removed, and the polycrystalline silicon layer is anisotropically etched by irradiating the laser beam 8a in HF3+H2 gas using the photoresist layer 5 as a mask. 4 exposed portions 10 are formed.
次に、第1図(d)に示すように、ホトレシス)N5を
剥離してから、シリコン酸化膜3の表面を厚さの5〜3
0%程度除去して、開孔部6の縁の円周部にテーパ9の
一部を残した後、アルミニウム配線層10を堆積して形
成する。Next, as shown in FIG. 1(d), after peeling off the N5 (photoresistor), the surface of the silicon oxide film 3 is coated to a thickness of 5 to 3
After removing approximately 0% and leaving a portion of the taper 9 at the circumferential portion of the edge of the opening 6, an aluminum wiring layer 10 is deposited and formed.
本実施例のエツチングとして第1図(b)〜(C)の光
照射工程をNH3+H2の反応性ガス中で行って、シリ
コン酸化膜3に開孔部6からの等方的に照射された部分
のカスエツチングを行ったが、直接引いレーザ光8aを
用いて光によるスパッタをしてもよい。As the etching in this example, the light irradiation steps shown in FIGS. 1(b) to 1(C) were performed in a reactive gas of NH3+H2, and the portions of the silicon oxide film 3 that were isotropically irradiated from the openings 6 were Although the above etching was carried out, optical sputtering may also be carried out using a direct laser beam 8a.
以上説明したように本発明は、レーザ光の光源から半導
体チップの開孔部に至る光路中に拡散透過体を置いてエ
ツチングすることにより、全表面が、清浄な状態で、絶
縁膜中に上部テーパを有する開孔部を形成できる効果が
ある。As explained above, in the present invention, by placing a diffusive transmitter in the optical path from the laser light source to the opening of the semiconductor chip and performing etching, the entire surface is kept clean while the upper part of the insulating film is etched. This has the effect of forming a tapered opening.
第1図<a)〜(d)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。
1・・・半導体基板、2.3・・・シリコン酸化膜、3
b・・・中底部、4・・・n形多結晶シリコン層、5・
・・ホトレジスト層、6・・・開孔部、7・・・すりガ
ラス板、8a・・・レーザ光、8b・・・拡散透過光、
9・・・テーパ、10・・・露出部、11・・・アルミ
ニウム配線層。
万1図
手続補正書 (自利 5゜
1、事件の表示 昭和62年特許願第040712号2
発明の名称 半導体装置の製造方法3、補正をする者
事件との関係 出 願 人件 所
東京都港区芝五丁目33番1号名 称 (423
) 日本電気株式会社代表者 関 本 忠 弘
4、代理人
住 所 〒108東京都港区芝五丁目37番8号住友三
田ビル
補正の対象
明細書の発明の詳細な説明の瀾。
補正の内容
明細書の第3頁第3行目から4行目の「形成された円筒
形の開口部の上面に、更に」を「円筒形の開口部を形成
するに先だち予め」に補正する。FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. 1... Semiconductor substrate, 2.3... Silicon oxide film, 3
b... Middle bottom portion, 4... N-type polycrystalline silicon layer, 5...
... Photoresist layer, 6... Opening portion, 7... Ground glass plate, 8a... Laser light, 8b... Diffuse transmitted light,
9...Taper, 10...Exposed portion, 11...Aluminum wiring layer. 1, 1, Indication of the case, Patent Application No. 040712, 1988, 2
Title of the invention Semiconductor device manufacturing method 3, relationship to the amendment person case Application Person Place
5-33-1 Shiba, Minato-ku, Tokyo Name (423)
) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent Address: Sumitomo Sanda Building, 37-8 Shiba 5-chome, Minato-ku, Tokyo 108 Detailed explanation of the invention in the revised specification. Amend "Additionally, on the upper surface of the formed cylindrical opening" in the third to fourth lines of page 3 of the description of the amendment to "prior to the formation of the cylindrical opening" .
Claims (1)
素子の電極または配線となる導体層を形成する工程を有
する半導体装置の製法方法において、前記絶縁膜の上に
該絶縁膜よりエッチング速度の遅い材料の層を堆積し、
開孔部を設けてマスクとする工程と、光の入射面が平坦
で射出面が微細凸凹を有する面である光拡散物体の板を
前記マスクの上方に置き上方からレーザ光を照射して前
記絶縁膜をその厚さの半分程度まで等方性エッチングを
行う行程と、前記光拡散物体を除いて前記開孔部の残り
の絶縁膜を異方性エッチングして前記絶縁膜の下である
前記導体層の露出させる工程と、前記マスクを除去し、
前記等方性エッチングされた絶縁膜部分の厚さが半分程
度になるまで前記記録を表面からエッチング除去する工
程と、前記導体層に接続し前記絶縁膜上に延在する上層
記録を形成する工程とを含むことを特徴とする半導体装
置の製造方法。In a method for manufacturing a semiconductor device, which includes a step of forming a conductive layer to serve as an electrode or wiring of a semiconductor element through an insulating film having an opening on a semiconductor substrate, a conductor layer having an etching rate lower than that of the insulating film is formed on the insulating film. Depositing layers of slow material;
A step of providing an aperture to form a mask, and placing a plate of a light diffusing object whose light entrance surface is flat and whose light exit surface has minute irregularities above the mask and irradiating the laser beam from above. isotropically etching the insulating film to about half its thickness; and anisotropically etching the remaining insulating film in the opening, excluding the light diffusing object, to remove the remaining insulating film under the insulating film. exposing the conductor layer and removing the mask;
a step of etching away the recording from the surface until the thickness of the isotropically etched insulating film portion is reduced to about half; and a step of forming an upper layer recording connected to the conductor layer and extending over the insulating film. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4071287A JPS63207151A (en) | 1987-02-23 | 1987-02-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4071287A JPS63207151A (en) | 1987-02-23 | 1987-02-23 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63207151A true JPS63207151A (en) | 1988-08-26 |
Family
ID=12588195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4071287A Pending JPS63207151A (en) | 1987-02-23 | 1987-02-23 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63207151A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000050198A1 (en) * | 1999-02-25 | 2000-08-31 | Seiko Epson Corporation | Method for machining work by laser beam |
-
1987
- 1987-02-23 JP JP4071287A patent/JPS63207151A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000050198A1 (en) * | 1999-02-25 | 2000-08-31 | Seiko Epson Corporation | Method for machining work by laser beam |
US6563079B1 (en) | 1999-02-25 | 2003-05-13 | Seiko Epson Corporation | Method for machining work by laser beam |
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