JPS6320125Y2 - - Google Patents
Info
- Publication number
- JPS6320125Y2 JPS6320125Y2 JP1986195159U JP19515986U JPS6320125Y2 JP S6320125 Y2 JPS6320125 Y2 JP S6320125Y2 JP 1986195159 U JP1986195159 U JP 1986195159U JP 19515986 U JP19515986 U JP 19515986U JP S6320125 Y2 JPS6320125 Y2 JP S6320125Y2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- layer
- type
- conductivity type
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案はツエナ・ダイオード、特にサブ・サー
フエイス・ツエナ・ダイオードの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a zener diode, particularly a sub-surf-eighth zener diode.
第１図に従来のサブ・サーフエイス・ツエナ・
ダイオードの模式断面図を示す。１はＮ型半導体
基板で、２はP+型の第１の拡散層、３はＰ型の
第２の拡散層、４はN+型の第３の拡散層である
（第１の拡散層２と第３の拡散層４の共通領域の
導電型はＮ型となるように各不純物濃度は調整さ
れているものとする）。この構造のツエナ・ダイ
オードは、降状が表面ではなくバルク中のａ面に
て起こるため表面の電荷等の影響から隔離される
ため大変にすぐれた温度ドリフト特性、低雑音特
性を持つが反面降伏がバルク中のａ面で起こるた
め接合から第２の拡散層３を通つてアノード電極
までのインピーダンスが非常に大きい、特に第２
の拡散層３の第３の拡散層の直下の部分ｂ（図中
ハツチングした部分）の抵抗が大きいことが支配
的であり、従つて動作抵抗が非常に大きいという
欠点を持つ。 Figure 1 shows the conventional sub-surf-eighth
A schematic cross-sectional view of a diode is shown. 1 is an N-type semiconductor substrate, 2 is a P + type first diffusion layer, 3 is a P type second diffusion layer, and 4 is an N + type third diffusion layer (first diffusion layer It is assumed that the concentration of each impurity is adjusted so that the conductivity type of the common region of the second and third diffusion layers 4 is N type). Zener diodes with this structure have very excellent temperature drift characteristics and low noise characteristics because the precipitation occurs on the a-plane in the bulk, not on the surface, so they are isolated from the effects of surface charges, etc., but on the other hand, they do not break down. occurs on the a-plane in the bulk, so the impedance from the junction to the anode electrode through the second diffusion layer 3 is very large, especially in the second diffusion layer 3.
The resistance of the portion b (hatched portion in the figure) immediately below the third diffusion layer of the diffusion layer 3 is predominant, and therefore the operating resistance is extremely large.
本考案は従来のサブサーフエイス・ツエナ・ダ
イオードの前記欠点を克服し、温度ドリフト特性
と雑音特性に優れかつ動作抵抗の低いヤエナ・ダ
イオードを提供することを目箇とする。 The present invention aims to overcome the above-mentioned drawbacks of the conventional sub-surf 8th Zena diode and provide a Yaena diode with excellent temperature drift characteristics and noise characteristics and low operating resistance.
次に、実施例をあげ、図面に従つて本考案を説
明すると、第２図は本考案の一実施例を示す模式
断面図で、５は半導体基板（導電型はＰ型又はＮ
型のいずれでもよい）、６はN-型エピタキシヤル
層、７はP+型埋込層（第１導電型の高濃度領
域）、８はエピタキシヤル層６の表面より拡散形
成されたP+型の第１の拡散層、９はエピタキシ
ヤル層６の表面より拡散形成されたＰ型の第２の
拡散層、１０はエピタキシヤル層６の表面より拡
散形成されたN+型の第３の拡散層である。本考
案は、第１図に示す従来のツエナ・ダイオードの
アノードとしてP+型埋込層７を追加接続して、
第３の拡散層１０の直下の部分の第２の拡散層の
部分の高抵抗を減少せしめツエナ・ダイオードと
しての動作抵抗を大幅に減少させるものである。
即ち、接合からアノード電極へ流れる電流は従来
のツエナ・ダイオードでは第１図のｂに非常に高
抵抗な部分を通るのに対し、第２図に示す本考案
では接合a′からの電流は第１の拡散層から低抵抗
の埋込層７を通りアノード電極に流れるため動作
抵抗は非常に小さくなる。しかも、本考案を実施
しても従来のサブ・サーフエイス・ツエナ・ダイ
オードの持つ温度ドリフト特性、低雑音電圧特性
を損なうことはないので、第１図に示す従来のツ
エナ・ダイオードの動作抵抗の大きいという欠点
を完全に解消することができるものである。な
お、以上の説明において導電型を互いに入れかえ
ても全く同様に成立することは言うまでもない。 Next, the present invention will be explained with reference to the drawings and examples. Fig. 2 is a schematic cross-sectional view showing one embodiment of the present invention, and 5 is a semiconductor substrate (conductivity type is P type or N type).
6 is an N - type epitaxial layer, 7 is a P + type buried layer (first conductivity type high concentration region), and 8 is a P + layer diffused from the surface of the epitaxial layer 6. 9 is a P type second diffusion layer formed by diffusion from the surface of the epitaxial layer 6, and 10 is an N + type third diffusion layer formed from the surface of the epitaxial layer 6. It is a diffusion layer. In the present invention, a P + type buried layer 7 is additionally connected as an anode of the conventional Zener diode shown in FIG.
This reduces the high resistance of the second diffusion layer directly below the third diffusion layer 10, and significantly reduces the operating resistance of the Zener diode.
That is, in the conventional Zener diode, the current flowing from the junction to the anode electrode passes through the extremely high resistance part b in Figure 1, whereas in the present invention shown in Figure 2, the current from the junction a' passes through the very high resistance part b in Figure 1. Since it flows from the diffusion layer 1 to the anode electrode through the low-resistance buried layer 7, the operating resistance becomes extremely small. Moreover, even if the present invention is implemented, the temperature drift characteristics and low noise voltage characteristics of the conventional sub-surface zener diode are not impaired, so the conventional zener diode shown in Fig. 1 has a large operating resistance. This drawback can be completely eliminated. It goes without saying that in the above description, even if the conductivity types are exchanged, the same holds true.
第１図は従来のサブ・サーフエイス・ツエナ・
ダイオードの一例を示す模式断面図である。
１……N-型半導体基板、２……P+型の第１の
拡散層、３……Ｐ型の第２の拡散層、４……N+
型の第３の拡散層。
第２図は本考案の一実施例を示す模式断面図で
ある。
５……半導体基板、６……N-型エピタキシヤ
ル層、７……P+型埋込層、８……P+型第１の拡
散層、９……Ｐ型第２の拡散層、１０……N+型
第３の拡散層。
Figure 1 shows the conventional sub-surf-eighth
FIG. 2 is a schematic cross-sectional view showing an example of a diode. 1... N - type semiconductor substrate, 2... P + type first diffusion layer, 3... P type second diffusion layer, 4... N +
Third diffusion layer of the mold. FIG. 2 is a schematic sectional view showing an embodiment of the present invention. 5... Semiconductor substrate, 6... N - type epitaxial layer, 7... P + type buried layer, 8... P + type first diffusion layer, 9... P type second diffusion layer, 10 ...N + type third diffusion layer.
Claims (1)
半導体基板上に形成された第２導電型の半導体層
と、前記半導体層の表面から前記高濃度埋込領域
にまで到達する深さを有する第１導電型の第１の
拡散層と、前記第１の拡散層と同じ導電型でかつ
該第１の拡散層より広く拡散され、その底面の全
面が前記高濃度領域内部に到達するように形成さ
れた低濃度の第２の拡散層と、前記第２の拡散層
の表面より内部に向けて前記第１の拡散層の表面
領域をおおうように拡散され、その底面が前記高
濃度埋込領域とは離間するように形成された第２
導電型の第３の拡散層とを有し、前記第３の拡散
層の表面および前記第２の拡散層の表面に夫々電
極を形成したことを特徴とするツエナ・ダイオー
ド。 A semiconductor layer of a second conductivity type formed on a semiconductor substrate selectively having a high concentration buried region of a first conductivity type, and a depth reaching the high concentration buried region from the surface of the semiconductor layer. a first diffusion layer of a first conductivity type, which has the same conductivity type as the first diffusion layer, is diffused more widely than the first diffusion layer, and whose entire bottom surface reaches inside the high concentration region; a low-concentration second diffusion layer formed in the second diffusion layer, and the second diffusion layer is diffused inward from the surface of the second diffusion layer to cover the surface area of the first diffusion layer, and the bottom surface thereof is formed in the high-concentration buried layer. The second area is formed so as to be separated from the
1. A Zener diode comprising a third diffusion layer of a conductive type, and electrodes are formed on a surface of the third diffusion layer and a surface of the second diffusion layer, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986195159U JPS6320125Y2 (en) | 1986-12-18 | 1986-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986195159U JPS6320125Y2 (en) | 1986-12-18 | 1986-12-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62122363U JPS62122363U (en) | 1987-08-03 |
| JPS6320125Y2 true JPS6320125Y2 (en) | 1988-06-03 |
Family
ID=31152793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986195159U Expired JPS6320125Y2 (en) | 1986-12-18 | 1986-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320125Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4835865A (en) * | 1971-09-03 | 1973-05-26 | ||
| JPS54128294A (en) * | 1978-03-29 | 1979-10-04 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-12-18 JP JP1986195159U patent/JPS6320125Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4835865A (en) * | 1971-09-03 | 1973-05-26 | ||
| JPS54128294A (en) * | 1978-03-29 | 1979-10-04 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62122363U (en) | 1987-08-03 |
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