JPS6320050B2 - - Google Patents
Info
- Publication number
- JPS6320050B2 JPS6320050B2 JP54162325A JP16232579A JPS6320050B2 JP S6320050 B2 JPS6320050 B2 JP S6320050B2 JP 54162325 A JP54162325 A JP 54162325A JP 16232579 A JP16232579 A JP 16232579A JP S6320050 B2 JPS6320050 B2 JP S6320050B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- present
- multiplier
- digital filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005070 sampling Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Processing Of Color Television Signals (AREA)
Description
【発明の詳細な説明】
本発明は、阻止周波数を自由に調整できると共
に、帯域阻止フイルタを容易に実現できるように
なつたデイジタル・フイルタに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter in which the rejection frequency can be freely adjusted and a band rejection filter can be easily realized.
第１図は本発明の基礎となつたデイジタル・フ
イルタのブロツク図であつて、１は信号入力端
子、２は信号出力端子、３は遅延回路、４は加算
器をそれぞれ示している。第１図のデイジタル・
フイルタにおいて、遅延回路の遅延時間をNTと
仮定する。たゞし、Ｎは零以外の正の整数であ
り、Ｔは標本化周期である。入力信号をｘ（ｔ）
を
ｘ（ｔ）＝Asin（ωt＋θ） (1)
（たゞし、Ａは振幅、θは位相、ωは角周波数）
とすると、出力信号ｙ（ｔ）は
ｙ（ｔ）＝ｘ（ｔ）＋ｘ（ｔ−NT）
＝Asin（ωt＋θ）
＋Asin（ωt＋θ−NωT）
＝2Acos（Ｎ／２ωT）sin（ωt
＋θ−Ｎ／２ωT） (2)
となる。阻止周波数は
cos（Ｎ／２ωT）＝０
となる角周波数ωで与えられ
ω＝（2k−１）π／NT (3)
（たゞし、ｋ＝１、２、……）
となる。こゝで、標本化周期Ｔは固定であり、Ｎ
は整数しかとり得ないので、第１図のデイジタ
ル・フイルタでは阻止周波数はＮおよびＴで定ま
る飛び飛びの点でしか得ることが出来ず、任意の
阻止周波数を設定することが出来なかつた。ま
た、第１図のものは阻止周波数と帯域として与え
ることが出来なかつた。 FIG. 1 is a block diagram of a digital filter that forms the basis of the present invention, in which 1 indicates a signal input terminal, 2 a signal output terminal, 3 a delay circuit, and 4 an adder. Figure 1 Digital
In the filter, the delay time of the delay circuit is assumed to be NT. However, N is a positive integer other than zero, and T is the sampling period. input signal x(t)
x(t)=Asin(ωt+θ) (1) (where A is the amplitude, θ is the phase, and ω is the angular frequency)
Then, the output signal y(t) is y(t)=x(t)+x(t-NT) =Asin(ωt+θ) +Asin(ωt+θ-NωT) =2Acos(N/2ωT)sin(ωt+θ-N/ 2ωT) (2). The stopping frequency is given by the angular frequency ω such that cos(N/2ωT)=0, and ω=(2k−1)π/NT (3) (so k=1, 2, . . . ). Here, the sampling period T is fixed and N
can only take on integers, so in the digital filter of FIG. 1, the rejection frequency can only be obtained at discrete points determined by N and T, and it is not possible to set an arbitrary rejection frequency. Moreover, in the case of FIG. 1, it was not possible to provide a stop frequency and a band.
本発明は、上記の欠点を解決するものであつ
て、阻止周波数の設定を任意に行うことが出来る
ばかりでなく、阻止周波数を帯域として与えるこ
との出来るデイジタル・フイルタを提供すること
を目的としている。そしてそのため、本発明のデ
イジタル・フイルタは、
入力信号を2NT時間（但し、Ｎは零以外の整
数、Ｔは標本化周期）遅延させて得られる第１の
信号を生成する手段３−１，３−２と、
上記入力信号をNT時間遅延させて得られる第
２の信号を生成する手段３−１と、
上記第２の信号が被乗数として入力され且つ乗
数を外部より設定可能な乗算器５と、
上記入力信号、第１の信号および乗算器５の出
力を加算処理する手段４，６と
を具備することを特徴とするものである。以下、
本発明を図面を参照しつつ説明する。 SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks, and aims to provide a digital filter that can not only arbitrarily set the rejection frequency but also provide the rejection frequency as a band. . Therefore, the digital filter of the present invention includes means 3-1, 3 for generating the first signal obtained by delaying the input signal by 2NT time (where N is an integer other than zero and T is the sampling period). -2; means 3-1 for generating a second signal obtained by delaying the input signal by NT time; and a multiplier 5 to which the second signal is input as a multiplicand and whose multiplier can be externally set. , means 4 and 6 for adding the input signal, the first signal, and the output of the multiplier 5. below,
The present invention will be explained with reference to the drawings.
第２図は本発明のデイジタル・フイルタで実現
できる振幅−周波数特性の１例を示す図、第３図
は本発明の１実施例のブロツク図である。 FIG. 2 is a diagram showing an example of amplitude-frequency characteristics that can be realized by the digital filter of the present invention, and FIG. 3 is a block diagram of one embodiment of the present invention.
第３図において、３−１と３−２は遅延回路、
４は加算器、５は定数±αの乗算器、６は加算器
もしくは減算器である。遅延回路３−１と３−２
のそれぞれは、NTの遅延時間を有するものであ
る。入力信号として式(1)の信号を入力すると、加
算器４の出力y1（ｔ）は
y1（ｔ）＝ｘ（ｔ）＋ｘ（ｔ−2NT）
＝2AcosNωTsin（ωt＋θ−ωNT） (4)
となる。また、乗算器５の出力をy2（ｔ）とする
と、
y2（ｔ）＝±αx（ｔ−NT）
＝±αAsin（ωt＋θ−ωNT） (5)
したがつて、加算器６の出力ｙ（ｔ）は
ｙ（ｔ）＝y1（ｔ）＋y2（ｔ）
＝Ａ（2cosNωT±α）sin（ωt
＋θ−ωNT） (6)
となり、第３図のデイジタル・フイルタの周波数
特性は、
Ｆ（ω）＝2cosNωT±α (7)
で与えられる。式(7)から判るように、αを零近く
に選択して調整すれば、式(3)で定められる阻止周
波数を高周波側もしくは低周波側に微調整するこ
とが出来る。また、αを２近くに選べば第２図に
示した阻止帯域にリプル（ripple）をもつた帯域
周波数フイルタを容易に実現することが出来る。
例えば本発明のデイジタル・フイルタを多周波信
号受信器に適用する場合、本発明のデイジタル・
フイルタで得られる阻止帯域を多周波信号の高群
あるいは低群周波数帯域に一致するように上記
α、Ｎを選択すれば、本発明のデイジタル・フイ
ルタで以て容易に多周波信号受信器の帯域阻止フ
イルタを構成できる。 In Fig. 3, 3-1 and 3-2 are delay circuits;
4 is an adder, 5 is a constant ±α multiplier, and 6 is an adder or a subtracter. Delay circuits 3-1 and 3-2
each has a delay time of NT. When the signal of equation (1) is input as the input signal, the output y 1 (t) of adder 4 is y 1 (t) = x (t) + x (t - 2NT) = 2AcosNωTsin (ωt + θ - ωNT) (4) becomes. Also, if the output of the multiplier 5 is y 2 (t), then y 2 (t) = ±αx (t-NT) = ±αAsin (ωt + θ-ωNT) (5) Therefore, the output of the adder 6 is y (t) is y(t)=y 1 (t)+y 2 (t) = A(2cosNωT±α) sin(ωt +θ−ωNT) (6), and the frequency characteristics of the digital filter in Fig. 3 are as follows. It is given by F(ω)=2cosNωT±α (7). As can be seen from equation (7), by selecting and adjusting α close to zero, the blocking frequency determined by equation (3) can be finely adjusted to the high frequency side or to the low frequency side. Furthermore, if α is chosen close to 2, it is possible to easily realize a band frequency filter with ripple in the stop band shown in FIG.
For example, when applying the digital filter of the present invention to a multi-frequency signal receiver, the digital filter of the present invention
If α and N are selected so that the stopband obtained by the filter matches the high or low frequency band of the multifrequency signal, the digital filter of the present invention can easily adjust the band of the multifrequency signal receiver. Blocking filters can be configured.
以上の説明から明らかなように、本発明によれ
ば、αの値によつて阻止周波数を任意に選択する
ことが出来、さらに阻止帯域幅および阻止帯域内
のリプルを任意の値に設定することが出来る。ま
た、本発明のデイジタル・フイルタをフイルタの
伝達関数において極をもつ（構造的にはフイード
バツク・ループをもつ）フイルタと組合せて種々
の周波数特性のフイルタを構成できることは勿論
であり、第３図は本発明の単なる１実施例にすぎ
ず、加算器６と加算器４の挿入順序、或は加算器
の構成は任意に選ぶことが出来る。なお、第３図
においては遅延回路３−１と３−２の連結点から
の出力を乗算器５に入力しているが、遅延回路３
−１，３−２とは別の遅延時間NTの遅延回路を
設け、この遅延回路の出力を乗算器に入力するよ
うにしても良い。 As is clear from the above explanation, according to the present invention, the stop frequency can be arbitrarily selected depending on the value of α, and the stop band width and the ripple within the stop band can be set to arbitrary values. I can do it. Furthermore, it is of course possible to configure filters with various frequency characteristics by combining the digital filter of the present invention with a filter having a pole in the filter transfer function (structurally having a feedback loop). This is just one embodiment of the present invention, and the order in which the adders 6 and 4 are inserted or the structure of the adders can be arbitrarily selected. In addition, in FIG. 3, the output from the connection point between delay circuits 3-1 and 3-2 is input to the multiplier 5, but the delay circuit 3
A delay circuit with a delay time NT other than -1 and 3-2 may be provided, and the output of this delay circuit may be input to the multiplier.
第１図は本発明のデイジタル・フイルタのブロ
ツク図、第２図は本発明のデイジタル・フイルタ
で実現できる振幅−周波数特性の１例を示す図、
第３図は本発明の１実施例のブロツク図である。
１……信号入力端子、２……信号出力端子、３
−１と３−２……遅延回路、４……加算器、５…
…定数±αの乗算器、６……加算器もしくは減算
器。
FIG. 1 is a block diagram of the digital filter of the present invention, and FIG. 2 is a diagram showing an example of amplitude-frequency characteristics that can be realized by the digital filter of the present invention.
FIG. 3 is a block diagram of one embodiment of the present invention. 1...Signal input terminal, 2...Signal output terminal, 3
-1 and 3-2...Delay circuit, 4...Adder, 5...
...multiplier with constant ±α, 6...adder or subtractor.
Claims (1)
整数、Ｔは標本化周期）遅延させて得られる第１
の信号を生成する手段３−１，３−２と、 上記入力信号をNT時間遅延させて得られる第
２の信号を生成する手段３−１と、 上記第２の信号が被乗数として入力され且つ乗
数を外部より設定可能な乗算器５と、 上記入力信号、第１の信号および乗算器５の出
力を加算処理する手段４，６と を具備することを特徴とするデイジタル・フイル
タ。[Claims] 1. The first signal obtained by delaying the input signal by 2NT time (where N is an integer other than zero and T is the sampling period)
means 3-1, 3-2 for generating a second signal obtained by delaying the input signal by NT time, the second signal is input as a multiplicand, and A digital filter comprising: a multiplier 5 whose multiplier can be set externally; and means 4 and 6 for adding the input signal, the first signal, and the output of the multiplier 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16232579A JPS5685926A (en) | 1979-12-13 | 1979-12-13 | Digital filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16232579A JPS5685926A (en) | 1979-12-13 | 1979-12-13 | Digital filter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5685926A JPS5685926A (en) | 1981-07-13 |
| JPS6320050B2 true JPS6320050B2 (en) | 1988-04-26 |
Family
ID=15752382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16232579A Granted JPS5685926A (en) | 1979-12-13 | 1979-12-13 | Digital filter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5685926A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5946370A (en) * | 1982-09-08 | 1984-03-15 | Daihatsu Motor Co Ltd | Compression ratio variable type internal-combustion engine |
| EP0105072B1 (en) * | 1982-10-06 | 1987-05-06 | Deutsche ITT Industries GmbH | Digital filter integrated circuit for the chrominance channel of a colour television apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5476048A (en) * | 1977-11-30 | 1979-06-18 | Nec Corp | Noncyclic variable filter |
-
1979
- 1979-12-13 JP JP16232579A patent/JPS5685926A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5476048A (en) * | 1977-11-30 | 1979-06-18 | Nec Corp | Noncyclic variable filter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5685926A (en) | 1981-07-13 |
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