JPS63200189A - Data transmission control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display control circuit that controls access to a frame memory that stores display data of a bitmap display device.

2. Description of the Related Art A conventional display control device for a bitmap display device is disclosed in, for example, Japanese Patent Application Laid-open No. 128572/1983.

FIG. 3 shows a block diagram of this conventional bitmap display device, in which 1 is a bit pattern generation circuit, 2.4 is a bitmap memory, 3 is an arithmetic circuit, 6 is a register, and 6 is a main control section. show.

In the conventional display control device configured as described above, the bit pattern generated by the bit pattern generating circuit 1 is written into the bit map memory 2, and the output of the bit map memory 4 and the output of the bit map memory 2 are transmitted to the arithmetic circuit 3. The result of the calculation is written into the bitmap memory 4. These operations follow read-modify-write instructions from the main control section 6.

Problems to be Solved by the Invention However, in the above configuration, when the bitmap memory 4 performs output for display and read-modify-write associated with data transfer at the same time, the data transfer ends within one frame. If not, the in-progress status of data transfer will be displayed on the display screen. This will be explained using FIG. In FIG. 3, the horizontal axis shows time, the vertical axis shows the vertical position of the screen scanning line, and the thick solid line shows the relationship between time and the screen scanning line position. Time t. The vertical flyback section ends at
Start scanning the first line. Time t.

The last line of the display section is scanned at time t.
The period up to 2 is the vertical retrace section. Here, number 1!
Consider the case where new image data is displayed in the section equivalent to the 42nd line. When displaying image data, data is transferred to the frame memory.

However, when the relationship between screen scanning lines and data transfer is as shown in FIG. 3, data transfer overtakes screen scanning lines. As a result, an intermediate state of data transfer processing may be displayed on the display screen. Similarly, in the horizontal direction of the screen scanning line, as shown in FIG. 4, an intermediate state of data transfer processing may be displayed on the display screen. For this reason, there was a problem in that the display screen was disturbed and flickered.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a data transfer control circuit that does not cause disturbances in the display screen due to image data transfer to a frame memory that stores display data of a bitmap display.

Means for Solving the Problems The present invention provides a vertical counter and a horizontal counter used to generate synchronization signals for a bitmap display, and a vertical counter and a vertical counter for storing the vertical and horizontal starting and ending points of a rectangular area for data transfer. a coordinate register, a horizontal coordinate register, vertical and horizontal area determination circuits that determine whether or not the position of a screen scanning line is within a rectangular area for data transfer based on the counter and the register, and each area determination circuit. This is a data transfer control circuit that includes a data transfer unit that is permitted to transfer data based on the result of a logical sum of the circuits.

Effect of the Invention With the above-described configuration, the present invention permits data transfer for displaying image data if the vertical counter indicating the vertical position of the screen scanning line is outside the rectangular area in which the data is transferred. do. Further, when the vertical position of the screen scanning line is within a rectangular area, data transfer is permitted when the horizontal counter indicating the horizontal position of the screen scanning line is outside the rectangular area. By controlling the data transfer unit in this manner, it is possible to eliminate disturbances and flickering on the display screen due to image data transfer.

Embodiment FIG. 1 shows a configuration diagram of a data transfer control circuit in an embodiment of the present invention. In Figure 1, 7 is CR
T display device; 8 is a frame memory for storing display data;
Reference numeral 9 indicates a synchronization signal generation unit that generates a synchronization signal and a display address generation request signal for the CRT display device, and reference numeral 10 indicates a synchronization signal generation unit that generates a synchronization signal and a display address generation request signal for the CRT display device, and reference numeral 10 performs data transfer in a rectangular area when data transfer is possible for the frame memory 8, updates display content, and simultaneously generates an address for data transfer. A data transfer unit 11 that generates a request signal generates a display address in synchronization with a display address request generated by the synchronization signal generation unit 9, and generates an address of a rectangular area according to an address generation request signal for data transfer generated by the data transfer unit. 12 is a vertical counter indicating the vertical position of a screen scanning line used in the synchronization signal generation section 9 to generate a vertical synchronization signal; 13 is a screen scanning line used in the synchronization signal generation section 9 to generate a horizontal synchronization signal. horizontal counter indicating the horizontal position of 1
4 stores the vertical end point coordinates of the rectangular area! ,register,
16 is a Ys register that stores the vertical start point coordinates of the rectangular area, 16 is an x8 register that stores the horizontal end point coordinates of the rectangular area, 17 is an X register that stores the horizontal start point coordinates of the rectangular area, and 18 is a Y8 register that is perpendicular to 14. The first comparator inputs the counter 12 and outputs "high" when the former is less than the latter, 19 is Y8 register 16 and vertical counter 1
2 and outputs "high" if the former is less than the latter.
comparator, 2o is x8 register 16 and horizontal counter 1
3 and outputs "high" if the former is less than the latter.
comparator, 21 is X, register 17 and horizontal counter 13
A fourth comparator 22 outputs "high" when the former is less than or equal to the latter; the output of the first comparator 18 is input to the set input, and the output of the second comparator 19 is input to the reset input. The first flip-flop, 23, has the output of the third comparator 2o as its set input, and the output of the fourth comparator as its reset input. 24, the output of the first flip-flop 22 and the output of the second flip-flop 23, and the gate 26 is a system path for writing parameters.

The operation of the data transfer control circuit of this embodiment configured as described above will be described below.

When displaying display data in the frame memory 8 on the CRT display device 7, a display address is generated from the address generator 11 in synchronization with the synchronization signal generator 9. Further, for synchronizing the CRT display device 7, a synchronizing signal generator 9 generates vertical and horizontal synchronizing signals. Here, when updating the display screen, the vertical end point and start point and the horizontal end point and start point indicating the rectangular area to be updated on the display screen are set via the system bus 26 in the Y8 register 14, the Ya register 16, and the x8 register, respectively. 16, X, is stored in the register 17 and the data transfer section is activated. The horizontal counter 13 updates the counter by clock input, and when it overflows, a carry is output. The vertical counter 12 updates its counter by the carry of the horizontal counter 13. Horizontal counter 13. According to the value of the vertical counter 12, horizontal and vertical synchronization signals are generated from the synchronization signal generating section. The horizontal counter 13 and the x8 register 16 are compared by the third comparator 2o, and if the former is greater than or equal to the latter, a "high" signal is output from the third comparator 2o. Otherwise, it outputs a "low" signal. Also, the horizontal counter 13 and x5 register 17 are set to the fourth
If the former is greater than the latter, the fourth comparator 21 outputs a "high" signal. Otherwise, it outputs a "low" signal. The output of the third comparator 2o is input to the set input of the second 7-lip-flop 23, and the output of the fourth
The output of the comparator 21 is input to the reset of the second flip 70 knob 23. Regarding the vertical counter 12, the vertical counter 12 and Y8 register 14, Y
The comparison with the s register 16 is performed in the first .s register. Second comparator 18.
I'll do it at 19. The output of the first comparator 18 is input to the set input of the first flip-flop 22, and the output of the first comparator 18 is inputted to the set input of the first flip-flop 22.
9 is input to the reset input of the first flip-flop 22. First and second flip-flops 22 and 23
The output will be explained with reference to FIGS.

In FIG. 6, the vertical axis represents the value of the vertical counter R, and the horizontal axis represents time. The comparison between the vertical counter 12 and the Yx register 14 by the first comparator 18 is to obtain point a in FIG.
The comparison of registers 16 corresponds to determining the points in FIG. Then, if data is transferred to the rectangular area from point a to point A across the vertical blanking interval, then
The status during data transfer is not displayed on the display screen.

This prevents screen disturbances and flickering caused by updating the display screen. Similarly, in Figure 6, the horizontal axis is the horizontal counter 1.
The value of 3, the vertical axis is time. The third comparator 2o
The purpose is to find point C in the figure, and the fourth comparator 21 corresponds to finding point d in FIG. If data is transferred to a rectangular area from point C to point d across the horizontal flyback section, the intermediate state due to data transfer is not displayed on the display screen. In particular, in this section, vertical counter 1
This is valid when 2 is within the rectangular area.

Therefore, the logical sum of the first 7-lip 70-tube 22 and the second 7-lip flop 23 determines the period during which the display screen will not be disturbed or flicker due to updating of the display screen during image data transfer to the rectangular area. It shows. The data transfer operation of the data transfer section 10 can be controlled by this signal.

As described above, according to this embodiment, the vertical counter 12 and Y
8 register 14 and Ys register 16 to confirm that it is outside the rectangular area, and also to confirm that the horizontal counter 13 is outside the rectangular area.
The display screen is updated by comparing the data with the X□ register 1e and the Xs register 17 and controlling the data transfer of the data transfer unit 10, which transfers data in the rectangular area, based on the logical sum of the data being outside the rectangular area. You can eliminate display disturbances and flickering.

As described in detail, according to the present invention, it is possible to prevent the display screen from being disturbed due to the transfer of image data to the frame memory that stores the display data of the bitmap display, and its practical effects are as follows. big.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a data transfer control circuit according to an embodiment of the present invention, Fig. 2 is a block diagram showing conventional data transfer, and Fig. 3 is an explanatory diagram showing vertical screen disturbance in rectangular area transfer. , FIG. 4 is an explanatory diagram showing horizontal screen disturbance during rectangular area transfer, FIG. 6 is an explanatory diagram of the operation in the vertical direction of an embodiment of the present invention, and FIG. 6 is an explanatory diagram of an embodiment of the present invention. FIG. 3 is an explanatory diagram of the operation in the horizontal direction. 1...Bit pattern generator, 2...
Bitmap memory, 3... Arithmetic circuit, 4...
...Bit map memory, 6...Register, 6...Main control unit, 7...CRT display device, 8...Frame memory, 9・・・・・・
Synchronization signal generation section, 10...Data transfer section, 11
...Address generator, 12...Vertical counter, 13...Horizontal counter, 14...
...Y8 register, 16...Y, register, 1
6...x8 register, 17...Xs
Register, 18, 19, 20, 21...Comparator, 22.23...7 Lip-flop, 24...
...OR game), 26. Old... System bus. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 2 Figure 4 Time

Claims (1)

[Claims] a frame memory for storing display data for a bitmap display; a vertical and horizontal counter for indicating the position of a screen display scanning line for the bitmap display; and a synchronization signal generator for generating a synchronization signal for the bitmap display from the vertical and horizontal counters. , a rectangular area on the frame memory indicated by a vertical start point and end point and a horizontal start point and end point, a vertical coordinate register and a horizontal coordinate register for storing them, and a frame memory indicated by the above vertical coordinate register and horizontal coordinate register. A data transfer unit that transfers data to the rectangular area above, a display address in synchronization with the synchronization signal generation unit, and an address of the rectangular area indicated by the vertical coordinate register and horizontal coordinate register in synchronization with the data transfer unit. a vertical area determination circuit that outputs a "high" signal from the vertical counter and the vertical coordinate register when the screen display scanning line is outside the rectangular area in the vertical direction; It consists of a horizontal area determination circuit that outputs a "high" signal when the screen display scanning line from the coordinate register is outside the rectangular area in the horizontal direction, and the output of the vertical area determination circuit and the output of the horizontal area determination circuit are A data transfer control circuit, wherein a data transfer operation of the data transfer unit is permitted based on a logical sum result.