[go: up one dir, main page]

JPS6319895A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPS6319895A
JPS6319895A JP16375986A JP16375986A JPS6319895A JP S6319895 A JPS6319895 A JP S6319895A JP 16375986 A JP16375986 A JP 16375986A JP 16375986 A JP16375986 A JP 16375986A JP S6319895 A JPS6319895 A JP S6319895A
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
ink
bridging
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16375986A
Other languages
Japanese (ja)
Inventor
忠義 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP16375986A priority Critical patent/JPS6319895A/en
Publication of JPS6319895A publication Critical patent/JPS6319895A/en
Pending legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、7「子機器類に使用するプリント配線板、特
に、部品実装用はんだ付は工程時におけるプリント回路
パターン間の架橋短絡防止方法に関するものである。
Detailed Description of the Invention (Field of Industrial Application) The present invention is directed to 7. A method for preventing bridging and short circuits between printed circuit patterns during the soldering process for printed wiring boards used in slave devices, especially for component mounting. It is related to.

〔従来の技術〕[Conventional technology]

従来のこの種のプリント配線板は、周知のように、エポ
キシ、フェノール等の熱硬化性樹脂と低ガラス布などの
補強材との組合せにより構成された基板の片面(片面形
プリント配線板の場合について説明する)に鋼等の導体
はくを張った導体缶h1層板の導体はく面上に感光レジ
ストを塗布したのち、写真法もしくはスクリーン印刷に
より回路パターンを記録し、エツチング法により所定パ
ターンを形成し、その上にソルダ・レジストやマークを
印刷したのち、穴加工/外形加工等を行い、フラックス
を塗布して完成する工程により製造されている。
As is well known, conventional printed wiring boards of this type are made of a combination of a thermosetting resin such as epoxy or phenol and a reinforcing material such as low-temperature glass cloth. After coating a photosensitive resist on the conductor foil surface of a conductor can (h1 layer plate) covered with a conductor foil such as steel, a circuit pattern is recorded by photography or screen printing, and a predetermined pattern is etched by an etching method. It is manufactured by a process in which a solder resist or mark is printed on it, holes are drilled/outlined, etc., and flux is applied to complete the process.

第2図に、従来のプリント配線板−ヒに、部品を搭載し
、該部品のピンをプリントパターン、ヒの穴に挿入して
、はんだ付けを行ったものの一例の要部拡大断面を示す
。図は、最も基本的な片面形プリント配線板の部品を搭
載する側を下面とし、はんだ付は側の面を−F面として
、表裏を反転させた状態を示す。各部1法は、明不のた
め、i0張して示し、中法比例関係は厳密でない。Sは
、回路パターンを形成する銅はくFを(FJさb)を張
った基板(厚さa)である。Rは、ソルダ・レジストで
、プリントパターンの所定のはんだ付けr定部分を除き
、パターンの全面およびエツチングされた基板裏面の露
出部分全面に施されている。Cは、ソルダ・レジストの
皮膜厚さを示す。また、しは搭載部品、Pは、その2個
のビン(部分的に2個のみを示す。通常は、複数個連続
する場合が多く、また、フラットビンの場合もある。)
である。ビンPは、プリントパターン上の所定の穴に挿
入され、はんだH付は作業により、ビンPとパターンの
所定部分との電気的接続が行われる。
FIG. 2 shows an enlarged cross-section of a main part of an example of a conventional printed wiring board in which components are mounted on the board, pins of the components are inserted into holes in the printed pattern, and soldered. The figure shows the most basic single-sided printed wiring board, with the side on which components are mounted being the bottom side and the soldering side being the -F side, with the front and back sides reversed. For clarity, each part 1 method is shown in i0 dilation, and the proportional relationship in the middle method is not strict. S is a substrate (thickness a) covered with a copper foil F (FJ Sab) forming a circuit pattern. R is a solder resist, which is applied to the entire surface of the pattern and the entire exposed portion of the etched back surface of the substrate, except for the predetermined soldering portions of the printed pattern. C indicates the film thickness of the solder resist. In addition, shi indicates the mounted parts, and P indicates the two bins (partially only two bins are shown. Usually, there are many consecutive bins, and there are also cases of flat bins.)
It is. The bottle P is inserted into a predetermined hole on the printed pattern, and the solder H is applied to electrically connect the bottle P and a predetermined portion of the pattern.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、最近は、一般的に通信機器や電子機器の
小形/高性能化指向に伴ない、プリント配線板への実装
も著しく小形/高密度化され、ディッピング等によるは
んだ付は工程における両ピン間の架橋短171(いわゆ
るブリッジング)が大きな問題となってきている。
However, in recent years, with the general trend toward smaller size/higher performance of communication equipment and electronic equipment, mounting on printed wiring boards has become significantly smaller/higher density, and soldering by dipping etc. is no longer required between both pins in the process. Short cross-linking 171 (so-called bridging) has become a major problem.

−4−なオ)ち、図において、両ピン間隔dが小さい場
合、パターン間隔eも極めて小さくなり、ビンPまわり
のけんだHが両ビン間に形成された凹部に濡れ性により
流入し易く、ここに流入すると表面張力により点線Ha
で示すように盛す−ヒリ、両ピン部のはんだ付は部Hに
ブリッジングを生ずるi+(佳作か極めて大きくなって
きた。
-4- E) In the figure, when the distance between both pins d is small, the pattern distance e also becomes extremely small, and the shards H around the bottle P easily flow into the recess formed between the two bottles due to wettability. , when it flows here, the dotted line Ha due to surface tension
As shown in the figure, the soldering of both pin parts causes bridging at part H.

例えば、集積回路(IC)等における連続する多数のビ
ンの間隔dは、初期の2.54+nmより1.18m!
11、さらに(1,75mm等と著しく縮小化され、こ
のため密集したパターン間隔eも0.3mm等のオーダ
が要求されるようになってきている。
For example, the interval d between a large number of consecutive bins in an integrated circuit (IC) etc. is now 1.18m, compared to the initial 2.54+nm!
11. Furthermore, the size has been significantly reduced to (1.75 mm, etc.), and as a result, the dense pattern spacing e is now required to be on the order of 0.3 mm, etc.

一方、銅はくのがさbを仮に35μmとすると、ソルダ
・レジスト皮MuさCζ5μI稈度であるため、凹部深
さは(35−5)=30μm程度となり、図からもブリ
ッジングの1iJ能性が大きいことがうかがわれる。
On the other hand, if the length b of the copper foil is assumed to be 35 μm, the solder/resist skin Mu is Cζ5 μI, so the recess depth is approximately (35-5) = 30 μm, and the figure also shows that the bridging capacity is 1iJ. It can be seen that the gender is large.

一個のプリント配線板において、極めて多数の微小ビン
間隔部分が存在するとき、製品の直行率(無条件合格率
)を低下させる不良原因の約半数は、このブリッジング
によるのが実情であり、また、ブリッジングは、PF買
上、いずわか不特定の箇所で生ずるため、修正のためそ
の不良箇所を発見するのに極めて多くの工数/時間を要
し、生産性/経済性を著しく低ドさせていた。
When a single printed wiring board has an extremely large number of micro-bin intervals, this bridging is actually responsible for approximately half of the causes of defects that reduce the direct pass rate (unconditional pass rate) of products. Since bridging occurs at unspecified locations during PF purchase, it takes an extremely large amount of man-hours/time to find the defective location for correction, which significantly reduces productivity/economic efficiency. was.

以トのような、ブリッジング現象発生の可能性を減少さ
せる目的で、例えば、“2重マスク法”が巴案されてい
る。第3図に、その第2図相当図を示す。第2図と同一
または相″IJ構成要素は同一符号で表わす。
For example, a "double mask method" has been proposed for the purpose of reducing the possibility of occurrence of the bridging phenomenon as described above. FIG. 3 shows a diagram corresponding to FIG. 2. IJ components that are the same or similar to those in FIG. 2 are designated by the same reference numerals.

この提案は、第2図における従来例のソルダ・レジスト
皮11Q Rのヒに必要箇所にのみ2次的に、本来の皮
膜Rと同様のソルダ・レジスト皮膜Raを小骨して2市
に施したものである。
This proposal is to apply a secondary solder resist film Ra similar to the original film R only to the necessary parts of the solder resist film 11Q R of the conventional example shown in Fig. It is something.

しかしながら、このような従来の提案例にあっては、前
記ブリッジング現象発生誘因である前記ビン間凹所にソ
ルダ・レジストの2重被覆を施しても、仮に、第2のソ
ルダ・レジスト皮膜厚さを本来の1次皮I+!2厚さd
と同程度とすると、前記凹所の深さは(b−2d)であ
り、b、dの値が第2図例と同一の場合、凹所深さは(
35−10)=25μmと5μmだけ浅くなり、前記従
来例の30μmに比し絶対値が減少した分だけの見掛は
的効果はあるが、実質的には、根本的に問題点を解消し
得る性質のものではないことは自明である。
However, in such conventional proposals, even if double coating of solder resist is applied to the recess between the bins, which is the cause of the bridging phenomenon, the thickness of the second solder resist film is The original primary skin I+! 2 thickness d
The depth of the recess is (b-2d), and if the values of b and d are the same as in the example in Fig. 2, the depth of the recess is (
35-10) = 25 μm, which is shallower by 5 μm and has an apparent effect due to the decrease in absolute value compared to 30 μm in the conventional example, but in reality, it does not fundamentally solve the problem. It is obvious that it is not something that can be obtained.

本発明は、以上のような従来例<nH記提案例を含む)
の問題点にかんがみてなされたもので、00記ブリツジ
ング現象の発生を根本的に解消すると共に、実装部品の
取付は位置決めにも便利な方7人を提供することを[4
的としている。
The present invention is applicable to the above-mentioned conventional example <including the proposed example described in nH)
This was done in consideration of the problem, and it is intended to fundamentally eliminate the occurrence of the 00 bridging phenomenon, and also to provide a convenient position for mounting components [4].
It has been the target.

(問題点を解決するためのf段〕 このため、本発明においては、導体はく回路パターンの
互いに近接するブリッジング防IF必要箇所に、発泡剤
を含有したインク皮膜を施したのち、所定温度で加熱す
ることにより、インク部分を導体はく厚さを超えて体積
膨張させることにより、前記目的を達成しようとするも
のである。
(Step F to solve the problem) Therefore, in the present invention, after applying an ink film containing a foaming agent to the locations where the bridging prevention IF is required close to each other in the conductor foil circuit pattern, the film is heated to a predetermined temperature. The purpose is to achieve the above object by heating the ink portion to expand the volume of the ink portion beyond the thickness of the conductor foil.

〔作用〕[Effect]

このため、両ビン間の凹所は完全に充填されるのみなら
ず、その間に盛り上って防壁を形成し、はんだが流入す
る怖かなくなるため、両ピン間のはんだ部のブリッジン
グは完全に防lトされ、また、その間に盛上って介在す
る防壁部分により搭載部品のセット時の位置決め川の助
けとなる。
Therefore, the recess between both pins is not only completely filled, but also rises up between them to form a barrier, eliminating the fear of solder flowing in, so the bridging of the solder part between both pins is completely completed. In addition, the raised barrier between the parts helps in positioning the mounted parts when setting them.

〔実施例〕〔Example〕

以ドに、発明を実施例に基ついて説明する。 Hereinafter, the invention will be explained based on examples.

第1図は、本発明を実施した片面形プリント配線板要部
を示ず航記第2.31A相当図であり、第2.3図と同
一または相当構成要素は同一符号で表わし、重複説明は
省略する。また、第2図における航記各寸法a、b、c
、d等もほぼ同様の値のものと仮定して説明する。
Figure 1 does not show the main parts of a single-sided printed wiring board embodying the present invention, but is a diagram corresponding to Figure 2.31A, and the same or equivalent components as in Figure 2.3 are denoted by the same reference numerals, and redundant explanations are given. is omitted. In addition, each dimension a, b, c in Figure 2
, d, etc. are assumed to have substantially similar values.

(構成) 点線で示すR1は、エツチング加工済みのプリント基板
上に、はんだ付は予定部分を除いて全面的に被覆された
ソルダ・レジスト皮膜Rのうち、ブリッジング防止を要
するパターン間微少すきま四部ヒに、選択的に重畳して
印刷被覆された、フェノールもしくはエポキシ系等の耐
熱性ソルダ・レジストインクであり、本発明の特徴は、
このインク中に適当な発泡剤を所定比率含有させたこと
にある。
(Structure) R1 indicated by the dotted line is the solder resist film R that is completely covered on the etched printed circuit board except for the areas scheduled for soldering, and there are four small gaps between patterns that require bridging prevention. The present invention is characterized by a heat-resistant solder/resist ink such as a phenol or epoxy-based solder resist ink that is selectively overlaid and printed on.
This ink contains a suitable blowing agent in a predetermined ratio.

(動作/作用) 以上のようなインクによる2次印刷を終ったのち、この
プリント配線板を、インク/発泡剤に特定された温度で
加熱すると、この2次印刷インク部分は、図示のように
、含有発泡剤によって体積膨張を生じ、四部を充填する
のみならず1.に方にも盛トって突出し、両ビン間に防
壁R2を形成して固化し、両ビン部のはんだ8間を完全
に遮断して、ブリッジングの可能性を消滅させる。
(Operation/Function) After completing the secondary printing using the ink as described above, when this printed wiring board is heated at a temperature specified for the ink/foaming agent, the secondary printing ink portion will be heated as shown in the figure. , the included blowing agent causes volumetric expansion, which not only fills the four parts, but also 1. It builds up and protrudes in both directions, forms a barrier R2 between the two bottles and solidifies, completely blocking the space between the solder 8 on both the bottles and eliminating the possibility of bridging.

さらにまた、これらの部分は視覚的にも[1立つ 、た
め、搭載品をセットするときの目印ともなり、従来のこ
の目的のための追加マーク印刷等を省略することもでき
る。
Furthermore, these parts also serve as visual marks when setting loaded items, and the conventional printing of additional marks for this purpose can be omitted.

(他の実施例) F記実施例においては、発泡剤を含有したソルダ・レジ
ストインクの2次皮膜について説明したが、本発明は、
これのみに限定されることかなく、発泡剤を含有した任
7位のインクを用い、面記1次皮膜に代って、これと被
覆順序を逆とし、あるいは、基板りに全く単独に適用し
ても同様の効果が得られる。
(Other Examples) In Example F, the secondary film of solder resist ink containing a foaming agent was explained, but the present invention
Without being limited to this, an ink containing a foaming agent can be used in place of the primary coating, with the coating order reversed, or applied entirely alone to the substrate. The same effect can be obtained.

また、プリント配線板は、片面形の場合について説明し
たが、両面形あるいは多層形にも適用し得ることは、も
ちろんである。
Moreover, although the printed wiring board has been described as a single-sided type, it goes without saying that it can also be applied to a double-sided type or a multilayer type.

〔発明の効果〕〔Effect of the invention〕

以上、説明してきたように、本発明によれば、■に近接
した導体は回路パターン間のすきまに、発泡したインク
の防壁が形成されるので、その間のはんだの架橋短絡を
完全に防止することができるようになり、プリント配線
板の実装作業の生産性と直行率とを大幅に向とすること
ができた。
As explained above, according to the present invention, a barrier of foamed ink is formed in the gap between the circuit patterns of the conductor in close proximity to the circuit pattern, so that cross-linking and short-circuiting of the solder between them can be completely prevented. As a result, the productivity and straight-through rate of printed wiring board mounting work have been significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明を実施したプリント配線板の要部拡大
断面図、第2図および第3図は、それぞれ従来例および
従来の一提案例の第1図相当図である。 S・・・・・・・・・基板 F・・・・・・・・・銅(導体)はく(回路パターン)
H−・・・・・・・・はんだ R・・・・・・・・・ソルダ・レジストR1・・・・・
・発泡性インク R2−−−−−−防壁 P・軸・・・・・・ビン し・・・・・・・・・実施部品
FIG. 1 is an enlarged sectional view of a main part of a printed wiring board embodying the present invention, and FIGS. 2 and 3 are views corresponding to FIG. 1 of a conventional example and a conventional proposed example, respectively. S...Substrate F...Copper (conductor) foil (circuit pattern)
H-...Solder R...Solder resist R1...
・Foaming ink R2---------Barrier P・Shaft...Bottling......Implemented parts

Claims (1)

【特許請求の範囲】[Claims]  プリント配線板の基板上の、互いに近接する導体はく
回路パターン間に、発泡剤を含有したインク皮膜を施し
、該プリント配線板を加熱することにより、前記インク
を体積膨張させたことを特徴とするプリント配線板。
An ink film containing a foaming agent is applied between adjacent conductor foil circuit patterns on a substrate of a printed wiring board, and the volume of the ink is expanded by heating the printed wiring board. Printed wiring board.
JP16375986A 1986-07-14 1986-07-14 Printed wiring board Pending JPS6319895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16375986A JPS6319895A (en) 1986-07-14 1986-07-14 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16375986A JPS6319895A (en) 1986-07-14 1986-07-14 Printed wiring board

Publications (1)

Publication Number Publication Date
JPS6319895A true JPS6319895A (en) 1988-01-27

Family

ID=15780161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16375986A Pending JPS6319895A (en) 1986-07-14 1986-07-14 Printed wiring board

Country Status (1)

Country Link
JP (1) JPS6319895A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6337689A (en) * 1986-07-31 1988-02-18 アイワ株式会社 Printed wiring board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5330670U (en) * 1976-08-23 1978-03-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5330670U (en) * 1976-08-23 1978-03-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6337689A (en) * 1986-07-31 1988-02-18 アイワ株式会社 Printed wiring board

Similar Documents

Publication Publication Date Title
US5210940A (en) Method of producing a printed circuit board
JP3289858B2 (en) Method of manufacturing multi-chip module and method of mounting on printed wiring board
JPS6319895A (en) Printed wiring board
JPS59148388A (en) Printed circuit board
CN111031704A (en) Method for adding solder resisting bridge between narrow and small IC pads on thick copper PCB
JPH0821764B2 (en) Printed board
JPS58132988A (en) Method of producing printed circuit board
KR19990002341A (en) Printed circuit board for mixing heterogeneous chip parts and manufacturing method
JP2003133714A (en) Printed-wiring board and manufacturing method thereof
JP2705154B2 (en) Manufacturing method of printed wiring board
JP2630097B2 (en) Method for manufacturing multilayer printed wiring board
JPS5882596A (en) Printed circuit board
JP2001251044A (en) Structure and method for mounting surface-mounting component
JPH01316994A (en) Solder resist printing ink of printed wiring board
TW202407820A (en) Package structure and method for fabricating the same
JP2001119119A (en) Printed circuit board and method for mounting electronic component
JP3855303B2 (en) Method for manufacturing printed wiring board
JPH0382096A (en) Soldering method
JPH04233800A (en) Printed circuit board with electrostatic shield and its manufacturing method
JPH027484Y2 (en)
JPH01238192A (en) printed wiring board
JPH0389596A (en) Printed circuit board
JPH01316993A (en) printed wiring board
JPH07202395A (en) Printed wiring board
JPS63204790A (en) printed wiring board