JPS63198884A - Test assisting circuit - Google Patents

Abstract

PURPOSE:To enable only a scan path which need to be put in shift operation to operate at the time of a test by supplying clocks to individual series- connected scan paths independently. CONSTITUTION:Scan paths 10 and 20 formed by connecting (n) stages and (m) stages are connected in series. Clocks are supplied to those scan paths 10 and 20 independently from clock input terminals 6a and 6b. For example, when a terminal 6b is held nonactive and only a terminal 6a is supplied with a clock, the (m)-stage scan path 20 keeps on holding data and the other path 10 shifts in optional (n)-bit data. Consequently, only a necessary scan path is put in operation at the time of the test, so data for the test are set and taken out of the scan path without any unnecessary shift operation and the test time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test auxiliary circuit for realizing testability of semiconductor devices.

[Conventional technology]

FIG. 3 shows a conventional scan path type test auxiliary circuit. In the figure, 1 is a scan register, 2 is a parallel input terminal, 3 is a parallel output terminal, 4 is a mode switching terminal, 5 is a serial input terminal, 6 is a clock input terminal, and 7 is a serial output terminal.

Next, the operation will be explained. A plurality of scan registers 1 are connected in series to form a shift register. That is, in FIG. 3, the shift register has n+m stages. In such a state, by setting the mode switching terminal 4 to serial shift mode, a serial shift is performed every time a clock is applied to the clock input terminal 6, and shift-out data is output to the shift output terminal 7, and the serial input is Shift in data from terminal 5.

On the other hand, by setting the mode switching terminal 4 to the parallel input mode, the data applied to the parallel input terminal 2 is taken into the scan register every time a clock is applied. Here, in any of the five modes, the value held by the scan register is output to the parallel output terminal 3.

The scan path can operate as described above, so shift in the test data in serial shift mode,
This data can be applied to the circuit under test through parallel output terminal 3, the response of the circuit under test can be taken into the scan register in parallel input mode, and this taken data can be shifted out to serial output terminal 7 in serial shift mode. .

Therefore, the number of terminals required for testing is smaller than the method of drawing out test signals to external terminals.

That is, in FIG. 3, only four terminals are required: mode switching terminal 4, serial input terminal 5, clock input terminal 6, and serial output terminal 7, and the semiconductor device can be constructed at low cost, so the scan path as described above is used as a test auxiliary circuit. It is used as.

[Problem that the invention seeks to solve]

However, the conventional test auxiliary circuit as described above is configured to shift all the data in the scan path at the same time, so it shifts all the data in the scan path at the same time. It is not possible to perform a test by rewriting only the scan path data. That is, to perform such a test, first shift in the same data held in the m-stage scan register, and
Then we have to shift out n bits of data,
A shift operation of rl+m1ffi was required. As described above, the conventional method involves an unnecessary shift operation, which has the problem of increasing test time and increasing the cost of testing semiconductor devices.

This invention was made to solve the above-mentioned problems, and allows test data to be set in the scan register without unnecessary shift operations.As a result, test time can be shortened and semiconductor devices can be manufactured at low cost. The purpose is to obtain a test auxiliary circuit that can be obtained.

[Means for solving problems]

The test auxiliary circuit according to the present invention divides a conventional scan path into a configuration in which a plurality of scan paths are connected in series, and makes it possible to independently apply a clock to each scan path. It is something.

[Effect]

The test auxiliary circuit according to the present invention can independently provide a clock to each scan path connected in series, so it does not operate scan paths that do not require a shift operation during testing. Only scan paths can be operated.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a scan register, 2 is a parallel input terminal, 3 is a parallel output terminal, 4 is a mode switching terminal, and 5
is a serial input terminal, (3a.

6b is a clock input terminal, and 7 is a serial output terminal.

FIG. 4 is a diagram in which the circuit in FIG. 1 is applied to a circuit network under test, where loa, 10b, and ioc are circuit blocks to be tested, lla, llb, and llc are input signal terminals, and 12a
, 12b are output signal terminals. Further, 13 and 14 are signal connection wirings from the circuit under test 10c to 10b and from the circuit under test 10b to 10a, respectively.

Next, the operation will be explained. In the circuit shown in FIG. 1, the scan path of the conventional circuit shown in FIG. It has been made possible. Therefore, if the same clock is supplied to the clock input terminals 5a and 5b, the same operation as the conventional circuit shown in FIG. 3 can be performed. In addition, the clock input terminal 6
If b is kept inactive, the m-stage scan path can continue to hold data, and any n-bit data can be shifted in to the n-stage scan path using the clock input terminal 6a. can do.

In other words, when performing a test by rewriting only the data of the n-stage scan path while retaining the data of the m-stage scan path, conventionally, n+m shift operations were required, but in this embodiment, n times All it takes is a shift operation. Especially n
This effect is large when <m.

An example where this configuration is particularly effective is shown in FIG.

In FIG. 4, when testing only block 1Ob in the circuit under test, it is assumed that the condition is such that the signal 13 from block IOC to 10b does not change. In this case, the contents of the m-stage shift register must not be changed because they affect the signal 13, and only the contents of the 1-stage shift register must be changed. In such a case, the scan path according to this embodiment can be easily realized because the clocks are separated.

The configuration according to this embodiment is also effective when only the contents of the m-stage shift register connected to the shift-out terminal 7 are shifted out. This example is also shown in FIG. In the figure, when testing only the circuit block 10a to be tested, it is assumed that the condition is such that the signal 14 from the block 10b to 108 is not changed. In this case, the contents of the n-stage shift register should not be changed because they affect the signal 14, and only the test result data in the m-stage shift register needs to be shifted out.

In the configuration according to this embodiment, this function can be easily realized by applying a clock to only the m-stage shift register. The separation of this shift-out operation is n>
The effect is particularly large in the case of m.

As shown in the above description, by dividing the shift clock applied to the scan path, redundant shift operations can be omitted, thereby reducing test time.

Although the embodiment shown in FIG. 1 shows a scan path that operates with a single-phase clock, the same effect as in the above embodiment can be obtained even if a scan path that operates with a two-phase clock is used. In addition, when using a scan path that operates with a two-phase clock,
As shown in Figure 2, one clock (terminal 6) is connected in common, and only the other clock is applied independently to each scan path (terminals 8a, 8b).
A similar effect can be obtained. The reason for this can be explained in FIG. That is, in FIG. 5, 21 and 23 are launches having a plurality of input terminals, 22 and 24 are launches, and latches 21 and 22 and latches 23 and 24 each form a 1-bit scan register la.

1b. 31 to 34 are latch clock terminals corresponding to each launch. In the configuration shown in FIG. 5, a 2-bit shift register can be constructed by connecting the clock terminals 31 and 33 and 32 and 34, respectively, and applying a two-phase clock to these terminals. Since this two-phase clock has terminals 31 and 33 as the first phase and terminals 32 and 34 as the second phase, the latches in the scan register hold the same contents after the shift operation. Let us now consider a case where terminals 32 and 34 are connected in common to provide the second phase clock, and only terminal 31 is provided with the first phase clock. In this case, the latched value in the scan register lb is the content of the launch 23, but since this is the same as the value launched in the latch 24, the output value of the scan register 1b does not change.

Next, consider a case where terminals 31 and 33 are connected in common to provide the first phase clock, and only terminal 32 is provided with the second phase clock. In this case, latch 23 in scan register lb
Although the contents of the scan register 1b are rewritten, the output of the scan register 1b remains held because the contents of the latch 24 do not change.

In the above explanation, the scan register 1a is operated by a shift operation, l
Although b is maintained, the same operation can be achieved by holding register 1a and shifting register 1b. When using scan registers that operate with two-phase clocks in this way, one clock can be connected in common and only the other clock can be applied independently to configure a scan path that can perform independent shift operations.

Therefore, if the above method is used, there is no need for twice as many clock terminals as there are individual scan paths, and there is an effect that the number of clock terminals can be reduced.

Also, although the examples in Figures 1, 2, and 4 show two scan paths connected in series, the same effect as above can be obtained even if two or more scan paths are connected. can get.

〔Effect of the invention〕

As described above, according to the present invention, clocks can be independently applied to multiple scan paths connected in series, and only the necessary scan paths can be operated during testing. Therefore, test data can be set on the scan path and test result data can be taken out from the scan path without unnecessary shift operations, which has the effect of shortening test time and obtaining an inexpensive semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a test auxiliary circuit according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a test auxiliary circuit according to another embodiment of the invention, FIG. 3 is a conventional test auxiliary circuit, and FIG. 1 is a diagram showing an example in which the circuit of FIG. 1 is applied to a circuit network under test, and FIG. 5 is a diagram showing an example of the configuration of a shift register for explaining the operation of the embodiment of FIG. 2. 1... Scan register, 2... Parallel input terminal, 3... Parallel output terminal, 4... Mode switching terminal, 5... Serial input terminal, 6, 8... Clock input terminal, 7 ...Serial output terminal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A test auxiliary circuit for inputting and outputting test data to and from the circuit under test, each consisting of a shift register of 1 bit or more, and multiple scan paths capable of parallel input and parallel output of 1 bit or more. A test auxiliary circuit characterized in that: are connected in series in the shift direction, and are provided with clock input terminals for independently applying shift clocks to the plurality of scan paths. (2) Claim 1, characterized in that the shift clock applied to the scan path is a two-phase clock.
Test auxiliary circuit described in section. (3) A claim characterized in that one of the two-phase clocks is commonly given to each scan path, and the other clock is given independently to each scan path. The test auxiliary circuit described in Section 2.